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| CXD1948R IEEE1394 Link Layer LSI for DVB and DSS For the availability of this product, please contact the sales office. Description The CXD1948R is a Link Layer LSI conforming to the IEEE1394 serial bus standard. During transmission, the MPEG2 transport stream is time stamped, transformed to IEEE1394 format and sent to the IEEE1394 Phy IC. During reception, the signal from IEEE1394 is kept in the built-in FIFO, synchronized to the time stamp value and output. This IC utilizes Apple Computer's Fire Wire technology. Features * Conforms to IEEE1394 serial bus standard * Supports DVB and DSS transport streams * Dedicated ports for asynchronous data/isochronous data * Isochronous data inserted from asynchronous data port * Smoothing buffer function * Large capacity FIFO Isochronous transmit/receive FIFO 960 x 32 bits Asynchronous transmit FIFO 30 x 33 bits Asynchronous receive FIFO 36 x 33 bits Isochronous Insert Packet Transmit Buffer 47 x 33 bits * CIP header automatic attachment/detection Applications * Digital interface for D-STB * Digital interface for D-VHS Structure Silicon gate CMOS IC 100 pin LQFP (Plastic) Absolute Maximum Ratings (Ta = 25C) Vss - 0.5 to +4.6 * Supply voltage VDD * Input voltage VI Vss - 0.5 to VDD + 0.5 * Output voltage VO Vss - 0.5 to VDD + 0.5 * Operating temperature Topr -20 to +75 * Storage temperature Tstg -55 to +150 Recommended Operating Conditions * Supply voltage VDD 3.0 to 3.6 * Operating temperature Topr -20 to +75 V V V C C V C Fire Wire is a registered trademark of Apple Computer Corporation, USA Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E96844-PS CXD1948R Contents 1. Block Diagram ............................................................................................................................................... 3 2. Pin Configuration ........................................................................................................................................... 4 3. Pin Description .............................................................................................................................................. 5 4. Electrical Characteristics ............................................................................................................................... 8 4-1. DC Characteristics ................................................................................................................................ 8 4-2. AC Characteristics ................................................................................................................................ 8 4-3. Timing Definitions ................................................................................................................................. 8 5. Isochronous Communication ......................................................................................................................... 9 5-1. Built-in FIFO ......................................................................................................................................... 9 5-2. Transport Stream I/F .......................................................................................................................... 10 5-3. Transport Stream Packet Split and Combine Functions ..................................................................... 18 5-4. Transport Stream ................................................................................................................................ 19 5-5. Isochronous Packet Structure ............................................................................................................ 20 5-6. Relationship between Additional Data and CFR Registers ................................................................ 27 5-7. 27MHz Time Stamp ............................................................................................................................ 27 5-8. Dummy Packet Transmission ............................................................................................................. 28 5-9. Time Stamp ........................................................................................................................................ 29 5-10. Error Processing ............................................................................................................................... 30 5-11. Late Processing ................................................................................................................................ 31 6. Asynchronous Communication .................................................................................................................... 31 6-1. Host/IF ................................................................................................................................................ 31 6-2. CFR .................................................................................................................................................... 34 6-3. Asynchronous Packet Transmission .................................................................................................. 44 6-4. Asynchronous Packet Reception ........................................................................................................ 47 6-5. CXD1948R Data Format .................................................................................................................... 52 6-6. Self-ID Packet Receiving Error Processing ........................................................................................ 62 7. Insert Packet ............................................................................................................................................... 63 7-1. Insert Packet Transmission ................................................................................................................ 63 7-2. Adding a Time Stamp to the Insert Packet ......................................................................................... 66 8. Link-Phy Communication ............................................................................................................................ 67 8-1. Link-Phy Interface Specifications ....................................................................................................... 67 8-2. Communication ................................................................................................................................... 67 9. Parallel Input/Output Port ............................................................................................................................ 74 10. System Configuration Example ................................................................................................................. 75 Annex. Corresponding Table for CFR Access Address And Host Interface I/O Data ..................................... 76 -2- 1. Block Diagram Asynchronous Transmit FIFO Transmitter Insert Packet Transmit Buffer Cycle Timer Host Host I/F D [0 : 3] CTL [0 : 1] PHY I/F LREQ SYSCLK PHY Asynchronous Receive Buffer Cycle Monitor Configuration Register -3- Isochronous Transmit/ Receive FIFO Header/Sync Detect/ Generate Receiver CRC MPEG2 Transporter Transport Data Stream I/F Link Core CXD1948R CXD1948R 2. Pin Configuration ERRFLAG AIWRITE PACKETGAP READREQ TEST18 AIREAD TEST19 TEST17 PORT4 PORT3 LREQ LPS CTL0 VDD TEST16 CTL1 TEST15 SYSCLK 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 D1 D2 VDD 50 TEST14 49 VSS 48 TEST13 47 TEST12 46 PORT2 45 PORT1 44 PORT0 43 TEST8 42 XINT 41 XW/R 40 XWAIT 39 XCS 38 VDD 37 ADDRESS0 36 ADDRESS1 35 ADDRESS2 34 ADDRESS3 33 ADDRESS4 32 ADDRESS5 31 ADDRESS6 30 X8/16 29 XRESET 28 VSS 27 TEST7 26 TEST6 VSS VSS 76 AICK 77 IFFULL 78 IFEMPTY 79 PACKETEN 80 VDD 81 CK27 82 IOEC 83 AIDT15 84 AIDT14 85 AIDT13 86 AIDT12 87 AIDT11 88 AIDT10 89 AIDT9 90 AIDT8 91 VSS 92 AIDT7 93 AIDT6 94 AIDT5 95 AIDT4 96 AIDT3 97 AIDT2 98 AIDT1 99 AIDT0 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 D3 DATA15 DATA9 DATA13 DATA8 DATA2 TEST0 VSS D0 DATA14 DATA3 DATA6 DATA11 DATA0 DATA7 DATA5 DATA10 DATA4 DATA12 DATA1 -4- TEST1 TEST2 TEST3 TEST4 TEST5 VSS VDD VSS CXD1948R 3. Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol Vss DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 VDD DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Vss TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 Vss XRESET X8/16 ADDRESS6 ADDRESS5 ADDRESS4 ADDRESS3 I/O -- I/O I/O I/O I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O I/O -- -- -- -- -- -- -- -- -- -- I I I I I I GND I/O data with host I/F BIT 15 I/O data with host I/F BIT 14 I/O data with host I/F BIT 13 I/O data with host I/F BIT 12 I/O data with host I/F BIT 11 I/O data with host I/F BIT 10 I/O data with host I/F BIT 9 I/O data with host I/F BIT 8 Power supply I/O data with host I/F BIT 7 I/O data with host I/F BIT 6 I/O data with host I/F BIT 5 I/O data with host I/F BIT 4 I/O data with host I/F BIT 3 I/O data with host I/F BIT 2 I/O data with host I/F BIT 1 I/O data with host I/F BIT 0 GND Test pin Test pin Test pin Test pin Test pin Test pin Test pin Test pin GND Master reset signal 0: Active; 1: Non-active I/O data with host I/F bus select signal 0: 8 bit; 1: 16 bit Host I/F address bus BIT 6 Host I/F address bus BIT 5 Host I/F address bus BIT 4 Host I/F address bus BIT 3 Description The test pins should be used open. -5- CXD1948R Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Symbol ADDRESS2 ADDRESS1 ADDRESS0 VDD XCS XWAIT XW/R XINT TEST8 PORT0 PORT1 PORT2 TEST12 TEST13 VSS TEST14 VDD SYSCLK VSS TEST15 TEST16 TEST17 TEST18 D3 D2 D1 D0 VSS CTL1 CTL0 LREQ VDD LPS TEST19 I/O I I I -- I O I O -- I/O I/O I/O -- -- -- -- -- I -- -- -- -- -- I/O I/O I/O I/O -- I/O I/O O -- O -- Host I/F address bus BIT 2 Host I/F address bus BIT 1 Host I/F address bus BIT 0 Power supply Host I/F chip select signal 0: Active; 1: Non-active Host I/F wait signal 0: Active; 1: Non-active Host I/F write/read signal 0: Write; 1: Read Host I/F interrupt signal 0: Active; 1: Non-active Test pin Parallel I/O port BIT0 Parallel I/O port BIT1 Parallel I/O port BIT2 Test pin Test pin GND Test pin Power supply Description Phy I/F system clock (49.152MHz) GND Test pin Test pin Test pin Test pin Phy I/F data bus BIT 3 Phy I/F data bus BIT 2 Phy I/F data bus BIT 1 Phy I/F data bus BIT 0 GND Phy I/F control bus BIT 1 Phy I/F control bus BIT 0 Phy I/F request signal Power supply Phy I/F Link power status signal Test pin The test pins should be used open. -6- CXD1948R Pin No. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol PORT3 PORT4 PACKETGAP READREQ ERRFLAG AIWRITE AIREAD VSS AICK IFFULL IFEMPTY PACKETEN VDD CK27 IOEC AIDT15 AIDT14 AIDT13 AIDT12 AIDT11 AIDT10 AIDT9 AIDT8 VSS AIDT7 AIDT6 AIDT5 AIDT4 AIDT3 AIDT2 AIDT1 AIDT0 I/O I/O I/O I O I/O I I -- I O O I/O -- I I I/O I/O I/O I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O I/O Parallel I/O port BIT3 Parallel I/O port BIT4 Description Timing signal for adding time stamp to inserted isochronous packet 0: Non-active; 1: Active Received packet synchronization reference signal 0: Non-active; 1: Active Packet error signal 0: Non-active; 1: Active Transport stream I/F data write enable signal 0: Non-active; 1: Active Transport stream I/F data read enable signal 0: Non-active; 1: Active GND Transport stream I/F clock Isochronous FIFO status output Isochronous FIFO status output 1: Full 1: Empty Transport stream I/F packet enable signal 0: Non-active; 1: Active Power supply Clock input for 27MHz time stamp (open when not in use) Transport stream I/F data bus control signal 0: Input; 1: Output Transport stream I/F data bus BIT 15 Transport stream I/F data bus BIT 14 Transport stream I/F data bus BIT 13 Transport stream I/F data bus BIT 12 Transport stream I/F data bus BIT 11 Transport stream I/F data bus BIT 10 Transport stream I/F data bus BIT 9 Transport stream I/F data bus BIT 8 GND Transport stream I/F data bus BIT 7 Transport stream I/F data bus BIT 6 Transport stream I/F data bus BIT 5 Transport stream I/F data bus BIT 4 Transport stream I/F data bus BIT 3 Transport stream I/F data bus BIT 2 Transport stream I/F data bus BIT 1 Transport stream I/F data bus BIT 0 The test pins should be used open. -7- CXD1948R 4. Electrical Characteristics 4-1. DC Characteristics Item Input voltage Input voltage Output voltage Output voltage Input leak current Input leak current Output leak current Symbol VIH VIL VOH VOL II1 II2 IOZ Conditions CMOS input cell CMOS input cell IOH = -4.0mA IOL = 4.0mA Bidirectional pin (input state) Normal input pin Tri-state pin (for high impedance state) VIN = VSS or VDD -40 -10 -40 VDD - 0.4 0.4 40 10 40 Min. 0.7VDD 0.2VDD (Ta = 25C, VSS = 0V) Typ. Max. Unit V V V V A A A 4-2. AC Characteristics Item Input setup Input hold Output delay Input setup Input hold Output delay Input setup Input hold Output delay Applicable pin AIDT [15 : 0], ERRFLAG, PACKETEN, IOEC, AIWRITE, AIREAD, PACKETGAP AIDT [15 : 0], ERRFLAG, READREQ D [3 : 0], CTL [1 : 0] D [3 : 0], CTL [1 : 0], LREQ ADDRESS [6 : 0], DATA [15 : 0], XCS, XWR DATA [15 : 0], XWAIT, XINT Symbol Normal clock Conditions Min. Tsu1 Th1 Td1 Tsu2 Th2 Td2 Tsu3 Th3 Td3 SYSCLK CL = 10pF AICK AIREAD AIWRITE 1 (VDD = 3.0 to 3.6V) Typ. Max. 10 CL = 10pF 5 5 2 2 Refer to P.31 ATF/CFR/IPF write timing ATF/CFR read timing 15 0 40 Unit ns ns ns ns ns ns 1 During asynchronous I/F, the reference clock is AIWRITE (transmit)/AIREAD (receive). 4-3. Timing Definitions Input Tsu Th reference clock Output Td -8- CXD1948R 5. Isochronous Communication The CXD1948R has a function which transmits and receives DVB and DSS transport stream data as isochronous packets. The communication of transport stream data with the DVB and DSS systems is performed using a dedicated I/O data bus and several control signal pins. (See below.) Further, it supports a wide variety of application I/F, including 8-bit data and 16-bit data, synchronous and asynchronous. Name AIDT PACKETEN ERRFLAG AIWRITE AIREAD READREQ AICK Width 16 1 1 1 1 1 1 in/out in/out in/out in/out in in out in Transport stream data bus Indicates a valid packet (valid: 1; invalid: 0) Indicates that the packet is an error (error: 1; no error: 0) Data write strobe signal Data read strobe signal Packet read request signal Clock for interface (during sync) Description 5-1. Built-in FIFO The CXD1948R has a built-in dedicated FIFO for isochronous communication. The FIFO capacity is 3840 bytes, and it can accumulate 20 packets worth of DVB transport stream. In order to actually use the built-in FIFO, the bank structure must be set. This is performed by the CFR PacketBanks register. -9- CXD1948R 5-2. Transport Stream Data I/F 5-2-1. Data Bus The data interface is 8 bit/16 bit, and switching is done by accessing the CFR AIDT16 register. (The default value is 8 bit.) 5-2-2. Transport Packet Size Data communication is done in transport stream packet units. The data size for one packet can be set optionally by accessing the S_PacketSize register on the CFR. S_PacketSize expresses the byte size of 1 source packet for isochronous communication. For DVB specifications, this is 192 (data 188 bytes, source packet header 4 bytes). 5-2-3. Isochronous Additional Data Optional data can be added to the transport stream packet when isochronous communication is performed. Setting of the additional data is done by setting the CFR AddSize and AddData1 to AddData10 registers. AddSize is a 4-bit register, and expresses the number of additional bytes for isochronous transmit/receive. AddData1 to AddData10 are each 8-bit registers, and express the additional data for isochronous transmit/receive. The default setting is no additional data. The additional data is inserted between the source packet header and the transport stream data. The smallest group of data that can be handed under IEEE1394 is 32 bits, so the setting must be such that the total of the transport stream data and additional data is a 32-bit unit. An example is shown below. Example of Isochronous Communication Setting When S_PacketSize = 192 and AddSize = 0 (example of setting for DVB) SPH Transport stream data 4 bytes 188 bytes When S_PacketSize = 144 and TxAddSize = 10 (example of setting for DSS) Additional data 10 Additional data 5 Additional data 1 Additional data 2 Additional data 3 Additional data 4 Additional data 6 Additional data 7 Additional data 8 Additional data 9 SPH Transport stream data 4 bytes 10 bytes 130 bytes - 10 - CXD1948R 5-2-4. Transmit Interface The CXD1948R is designed for use not only in transmitting an entire input transport stream, but also in transmitting one program only in the stream. The packet for transmission is selected through PACKETEN input as in the diagram below. Moreover, constraints are imposed in the packet intervals of streams that can be input to the CXD1948R. Each time the CXD1948R receives one packet of transport stream data, it adds time stamp data and data from the host I/F, and there must be an interval of 500ns or more for this processing. The timing is illustrated below. Also, the PACKETEN input signal must input "HIGH" while the first data of the transport stream packet is being sent. The maximum period for PACKETENABLE signal high is the period that the transport stream packet data is valid. The timing charts for synchronous/asynchronous interface are shown below. Transmit Interface Limits AIDT MPEG2 transporter PACKETEN CXD1948R Transmission of Program A AIDT A B A A B A A PACKETEN 500ns (min) - 11 - CXD1948R Transmit Interface (for sync mode/8 bit/Nbyte) AICK PACKETEN Don't Care AIWRITE AIDT Don't Care 0 first data taken in 1 2 second data taken in 3 ******** N-3 N-2 N-1 Don't Care ERRFLAG Valid interval for transport stream packet Sync interface mode is obtained by setting the CFR AsyncAI register to 0. (The default is 0.) The CXD1948R identifies the first data of the transport stream packet by detecting that the PACKETEN signal has gone from low to high. There is no particular need to input the PACKETEN signal after the first data. The size of the data taken in as valid data is equal to the value set in the CFR S_PacketSize register, decreased by 4 and by the value set in the AddSize register. The timing for taking in of the data internally is done by AICK rise when AIWRITE is high. The AIWRITE signal is used as the enable signal, so the interval that the AIWRITE signal is high relative to one data must be one AICK clock interval. The interval that the AIWRITE signal is low relative to one data is not specified. The limits on AICK input frequency are given below. For 8-bit data input: 40MHz (Max.), 2MHz (Min.) For 16-bit data input: 20MHz (Max.), 2MHz (Min.) The ERRFLAG input during transmit can be made valid by setting the CFR ErrBitEnable register to 1. (The default is 0.) The CXD1948R identifies the subject packet as an error if the ERRFLAG input is high for even one data during transport stream packet valid interval. The switching timing for ERRFLAG input can be changed in the same way as data switching timing, with AIWRITE signal rise. - 12 - CXD1948R Transmit Interface (for asynchronous mode/8 bit/Nbyte) AIWRITE PACKETEN Don't Care AIDT Don't Care 0 first data taken in 1 2 second data taken in 3 ******** N-3 N-2 N-1 Don't Care ERRFLAG Valid interval for transport stream packet Asynchronous interface mode is obtained by setting the CFR AsyncAI register to 1. (The default is 0.) The CXD1948R identifies the first data of the transport stream packet by detecting that the PACKET_EN signal has gone from low to high. There is no particular need to input the PACKET_EN signal after the first data. The size of the data taken in as valid data is equal to the value set in the CFR S_PacketSize register, decreased by 4 and by the value set in the AddSize register. The timing for taking in of the data internally is done by AIWRITE rise. The AIWRITE input is used as the clock, so there must be one AIWRITE input rising edge relative to one data. AIWRITE input duty is not specified, but the AIWRITE input must continue to be input evenly as the clock even outside of the transport stream packet valid interval. The limits on AIWRITE input frequency are given below. For 8-bit data input: 20MHz (Max.), 1MHz (Min.) For 16-bit data input: 10MHz (Max.), 1MHz (Min.) The ERRFLAG input during transmit can be made valid by setting the CFR ErrBitEnable register to 1. (The default is 0.) The CXD1948R identifies the subject packet as an error if the ERRFLAG input is high for even one data during transport stream packet valid interval. The switching timing for ERRFLAG input can be changed in the same way as data switching timing, with AIWRITE signal rise. - 13 - CXD1948R 5-2-5. Receive Interface The CXD1948R supports two modes; one in which data is output based on the time stamp value added to the transport stream packet during transmission, and one in which the data is output consecutively as soon as it is ready, without using the time stamp. When output is based on the time stamp value, the actual output timing is done using a value which is the time stamp value with a fixed delay added. This is done in order to keep the packet intervals even on the transmit and receive sides. When the time stamp value is not used for output, data output begins when the packet has completely arrived at the receive side. In this case, the time required for the packet to be sent and arrive completely at the receive side varies for each isochronous cycle, and packet interval on the transmit side can not be guaranteed. The timing is shown below. The mode in which the time stamp is not used can be set by setting the CFR TmsDis register to 1. (The default is 0.) Receive Interface AIDT D-VHS system PACKETEN CXD1948R Transmit I/F AIDT 1 2 3 4 5 PACKETEN Time stamp added timing Receive I/F Time stamp function used 1 2 3 4 AIDT PACKETEN Fixed delay Time stamp function not used 1 2 3 4 5 AIDT PACKETEN Time when packet 1 output is ready - 14 - CXD1948R Receive Interface (for sync mode/8 bit/Nbyte) AICK READREQ PACKETEN AIREAD AIDT Don't Care 0 1 2 ******** N-3 N-2 N-1 Don't Care ERRFLAG Valid interval for transport stream packet Sync interface mode is obtained by setting the CFR AsyncAI register to 0. (The default is 0.) The CXD1948R outputs the first data of the transport stream packet by changing the READREQ output signal and PACKETEN output signal from low to high when the packet has been completely received and is ready for output. The READREQ output signal goes low when the first data is output. The same as for transmit, the result of subtracting 4 and the value set in the AddSize register from the value set in the CFR S_PacketSize register is used as the size of the valid data output in one packet. The timing is done by the AICK rise when AIREAD is high. The AIREAD signal is used as the enable signal, so the interval that the AIREAD signal is high relative to one data must be one AICK clock interval. The interval that the AIREAD signal is low relative to one data is not specified. The limits on AICK input frequency are given below. For 8-bit data input: 40MHz (Max.), 2MHz (Min.) For 16-bit data input: 20MHz (Max.), 2MHz (Min.) The ERRFLAG input during receive can be made valid by setting the CFR ErrBitEnable register to 1. (The default is 0.) The CXD1948R outputs the ERRFLAG at high during the valid interval if the output transport stream packet is an error. The switching timing for ERR_FLAG input can be changed in the same way as data switching timing, with AIREAD signal rise. - 15 - CXD1948R Receive Interface (for asynchronous mode/8 bit/Nbyte) READREQ PACKETEN AIREAD AIDT Don't Care 0 1 2 ******** N-3 N-2 N-1 Don't Care ERRFLAG Valid interval for transport stream packet Sync interface mode is obtained by setting the CFR AsyncAI register to 0. (The default is 0.) The CXD1948R outputs the first data by changing the READREQ output signal and PACKETEN output signal from low to high when the packet has been completely received and is ready for output. The READREQ output signal goes low when the first data is output. The same as for transmit, the result of subtracting 4 and the value set in the AddSize register from the value set in the CFR S_PacketSize register is used as the size of the valid data output in one packet. The timing is done by the AIREAD signal rise. The AIREAD signal is used as the clock, so there must be one AIREAD input rising edge relative to one data. AIREAD input duty is not specified, but the AIREAD input must continue to be input evenly as the clock even outside of the transport stream packet valid interval. The interval that the AIREAD signal is low relative to one data is not specified. The limits on AICK input frequency are given below. For 8-bit data input: 20MHz (Max.), 1MHz (Min.) For 16-bit data input: 10MHz (Max.), 1MHz (Min.) The ERRFLAG input during receive can be made valid by setting the CFR ErrBitEnable register to 1. (The default is 0.) The CXD1948R outputs the ERRFLAG at high during the valid interval if the output transport stream packet is an error. The switching timing for ERR_FLAG input can be changed in the same way as data switching timing, with AIREAD signal rise. - 16 - CXD1948R 5-2-6. Using the ERRFLAG Pin The CXD1948R can function as a transport stream data interface using error information. Concretely, this is done using the ERRFLAG pin. Like other transport stream data interfaces, the ERRFLAG pin is a bidirectional pin. I/O switching is performed by the CFR IGFMode register. Also, ERRFLAG control is performed by the CFR ErrBitEn and ErrOutEn registers. The settings when using ERRFLAG during transmit and receive are given below. Transmit settings The ERRFLAG input can be made valid by setting the CFR ErrBitEn register to "1". (The default is "0".) In order to add the error information provided by ERRFLAG to an isochronous packet and transmit this information, the added data must be 4 bytes or more. Concretely, the CFR AddSize register value must be 4 or larger. Both of the conditions below must be met to send error information using the ERRFLAG pin during transmit. (1) The ErrBitEn register is 1. (2) The AddSize register is 4 or higher. Receive settings The ERRFLAG output can be made valid by setting the CFR ErrOutEn register to "1". (The default is "0".) The CXD1948R handles received packet errors in two ways as follows. (1) Packets with error information added to the transport stream data In this case, the error information must be added to the received isochronous packet. In addition, the CFR ErrBitEn register must be set to 1. (2) Error packets occurring during isochronous communication These errors refer to packets received with non-consecutive DBC values due to CRC errors or Late processing during transmit. In this case, only the CFR ErrOutEn register is set. Setting this register to "1" inserts an error packet between packets with non-consecutive DBC values. As a result, one packet of ERRFLAG = 1 data is read by the transport stream data interface. If the ErrOutEn register is set to 0, this processing is not performed. Non-consecutive DBC values also result when the receive FIFO overflows, and the processing is the same in these cases as well. - 17 - CXD1948R 5-3. Transport Stream Packet Split and Combine Functions The CXD1948R supports split and combine functions in order to use the bus bandwidth effectively. Concretely, the input transport stream packet can be split or combined according to the input rate and transmitted as an isochronous packet. The minimum size which can be split on the CXD1948R is one data block. For DVB specifications, one data block consists of 24 bytes, which means that 1 packet can be divided into eighths for transmission. The maximum size which can be combined is 15 packets. However, if the number of packets which can be transmitted in that cycle is smaller than the number that can be combined, all the packets present are combined in the transmission FIFO buffer and transmitted. The number of data blocks to be transmitted in one isochronous cycle is set before hand according to the stream peak rate. This is done by setting values in the CFR NOSP and NODB registers. The number of transmit source packets in one isochronous cycle is expressed by NOSP, and the number of transmit data blocks in one isochronous cycle is expressed by NODB. The default values are NOSP = 0001 and NODB = 000, for transmission of one source packet in one isochronous cycle. Always be sure to set either NOSP or NODB to 0. If the isochronous transmission parameters are not set such that the transmission rate is greater than the input stream peak rate, the FIFO buffer may fail. Example of Isochronous Transmit using Packet Split and Combine Functions I E MPEG2 transporter t s r t CXD1948R P l a r h a n e L t s IEEE1394 Isochronous o r t1 w a r n e r s a 2 3 t s 1 t r p / r 1 1 a l 2 1 a 2 2 n 3 i 2 n 3 s t p s H t s I I i r t E s g 4a r E o h n e E c s a 1 h 1 2 3 5 6 7 8 9 t c 2 t r o 1 a 2 m 2 p3 a 3 n 4 b 7 5 s i c s r 1 4 5 a6 n 8 - 18 - CXD1948R 5-4. Transport Stream Data Bandwidth The bandwidths on which transport stream data can be transmitted on the CXD1948R are illustrated below. DVB NOSP value 0000 0000 0000 0001 0010 0011 0100 0101 NODB value 001 010 100 000 000 000 000 000 No. of transmit data 1 data block 2 data blocks 4 data blocks 1 source packet 2 source packets 3 source packets 4 source packets 5 source packets Transmittable data rate 1.5Mbps 3.0Mbps 6.0Mbps 12.0Mbps 24.0Mbps 36.0Mbps 48.1Mbps 60.1Mbps DSS NOSP value 0000 0000 0001 0010 0011 0100 0101 0110 NODB value 001 010 000 000 000 000 000 000 No. of transmit data 1 data block 2 data blocks 1 source packet 2 source packets 3 source packets 4 source packets 5 source packets 6 source packets Transmittable data rate 2.2Mbps 4.4Mbps 8.9Mbps 12.0Mbps 26.8Mbps 35.8Mbps 44.8Mbps 53.7Mbps Transmittable data rate Addsize = Ah 2.0Mbps 4.1Mbps 8.3Mbps 16.6Mbps 24.9Mbps 33.2Mbps 41.6Mbps 49.9Mbps Addsize = 0h 2.2Mbps 4.4Mbps 8.9Mbps 17.9Mbps 26.8Mbps 35.8Mbps 44.8Mbps 53.7Mbps - 19 - CXD1948R 5-5. Isochronous Packet Structure The basic isochronous packet structure supported by the CXD1948R is illustrated below. On the CXD1948R, CIPHeaders 1 and 2 are automatically attached/detected in conformity to AV protocol. Also, a source packet header is automatically added/detected on the transport stream packet based on the MPEG Data Transmission for IEEE1394 Digital Interface specifications proposed in DVB-SMI. When one source packet is transmitted in one isochronous cycle, 1st quadlet is 1394Header, 2nd quadlet is Header_CRC (added at Link Core), 3rd quadlet is CIPHeader1, 4th quadlet is CIPHeader2, 5th quadlet is source packet header and 6th quadlet and after is the data area. The final quadlet is Data_CRC (added at Link Core). When a dummy packet is transmitted, there are only 1394Header, Header_CRC, CIPHeader1, CIPHeader2 and Data_CRC. Basic Structure 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1394Header data length tag Header CRC CIPHeader1 CIPHeader2 SPHeader 00 10 SID FMT Reserved TF DBS FN QPC FDF TimeStamp SPH reserved channel reserved speed sy DBC Data Data_CRC Note: The diagonally shaded areas ( ) for 1394Header and CIPHeader1 and 2 are attached automatically by the CXD1948R. Other areas are set from the external microcomputer via the host I/F. In transmission from the CXD1948R to an IEEE 1394PHYIC, the four bits marked "reserved" and "speed" of the 1394Header are automatically replaced by "tcode". - 20 - CXD1948R 1394Header Fields Field Name data_length Description Indicates the byte length of data from CIPHeader1. Type of format for data transferred as isochronous packet. 00: no Header 01: format defined by AV protocol 10: Reserved 11: Reserved Channel number used by the transmitted packet. Defines transfer speed. 00: 100Mbit/s 01: 200Mbit/s 10: 400Mbit/s 11: Undefined The CXD1948R supports "00" and "01". This field is defined by the application. tag channel speed sy Note: The Link Core must be informed of the communication speed in the case of isochronous communication, so [5 : 4] of [7 : 4], where a tCode is inserted, is used as the speed code. This is replaced with tCode (1010) at the Link Core. CIPHeader1 Fields Field Name SID DBS FN QPC SPH Description The CXD1948R Node ID. (0 to 3Fh) The number of quadlets transferred in one isochronous packet. For DVB specifications, this is "00000110b" and for DSS specifications, "00001001b". Indicates how many data blocks a source packet is divided into. The number of quadlets added to an incomplete packet when the source packet is split. Fixed at "0h" on the CXD1948R. Expresses whether a source packet header is used or not. Fixed at "1" on the CXD1948R. Increased by one for each data block. This is a free run continuity counter. When multiple data blocks are to be sent as a single isochronous packet, indicates the value for the first data block. DBC CIPHeader2 Fields Field Name FMT TF FDF Description Data format ID. This is "100000b" for DVB and "100001b" for DSS specifications. Indicates whether data is time-shifted. 1 if time-shifted; 0 if not time-shifted. Used in application defined by FMT. The value set via the host I/F is input as is on the CXD1948R. - 21 - CXD1948R SPHeader fields Field Name Reserved TimeStamp Description The value set via the host I/F is input as is on the CXD1948R. This is the value of the time that the transport stream packet arrived at the CXD1948R plus the fixed delay value. 5-5-1. DVB Format The DVB format supported by the CXD1948R is described below. The CFR S_PacketSize and AddSize registers are set as shown below when using the CXD1948R in DVB format. S_PacketSize: 0C0h AddSize: 0h Next, the NOSP and NODB registers are set. These determine how many data are to be transmitted/received in one isochronous cycle. The structures of isochronous packets for transmit/receive of data consisting of 1 source packet, 4 data blocks or 2 source packets in one isochronous cycle are illustrated below. DVB/Isochronous Packet Structure (1 source packet) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data_length 1394Header 00C8h tag Header_CRC CIPHeader1 CIPHeader2 SPHeader 00 10 SID FMT 20h Reserved data0 data1 TF DBS 06h FN 11 QPC 000 FDF TimeStamp data2 data3 SPH channel reserved speed sy reserved DBC 1 Data (188 bytes) data184 data185 Data_CRC data186 data187 Note: The diagonally shaded areas ( ) for 1394Header and CIPHeader1 and 2 are attached automatically by the CXD1948R. Other areas are set from the external microcomputer via the host I/F. In transmission from the CXD1948R to an IEEE 1394PHYIC, the four bits marked "reserved" and "speed" of the 1394Header are automatically replaced by "tcode". - 22 - CXD1948R DVB/Isochronous Packet Structure (4 data blocks) (First half data) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1394Header data_length 0068h tag Header_CRC CIPHeader1 CIPHeader2 SPHeader 00 10 SID FMT 20h Reserved data0 data1 TF DBS 06h FN 11 QPC 000 FDF TimeStamp data2 data3 SPH channel reserved speed sy reserved 1 DBC Data (92 bytes) data88 data89 Data_CRC data90 data91 (Second half data) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1394Header data_length 0068h tag Header_CRC CIPHeader1 CIPHeader2 00 10 SID FMT 20h data92 data96 TF data93 data97 DBS 06h FN 11 QPC 000 FDF data94 data98 data95 data99 SPH channel reserved speed sy reserved 1 DBC Data (96 bytes) data184 data185 Data_CRC data186 data187 Note: The diagonally shaded areas ( ) for 1394Header and CIPHeader1 and 2 are attached automatically by the CXD1948R. Other areas are set from the external microcomputer via the host I/F. In transmission from the CXD1948R to an IEEE 1394PHYIC, the four bits marked "reserved" and "speed" of the 1394Header are automatically replaced by "tcode". - 23 - CXD1948R DVB/Isochronous Packet Structure (2 source packets) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1394Header data_length 0184h tag Header_CRC CIPHeader1 CIPHeader2 SPHeader 00 10 SID FMT 20h Reserved data0 data1 TF DBS 06h FN 11 QPC 000 FDF TimeStamp data2 data3 SPH channel reserved speed sy reserved 1 DBC Data (188 bytes) data184 SPHeader Reserved data0 data185 data186 TimeSramp data187 data1 data2 data3 Data (188 bytes) data184 data185 Data_CRC data186 data187 Note: The diagonally shaded areas ( ) for 1394Header and CIPHeader1 and 2 are attached automatically by the CXD1948R. Other areas are set from the external microcomputer via the host I/F. In transmission from the CXD1948R to an IEEE 1394PHYIC, the four bits marked "reserved" and "speed" of the 1394Header are automatically replaced by "tcode". - 24 - CXD1948R 5-5-2. DSS Format The DSS format supported by the CXD1948R is described below. The interface with the system and the CFR setting differ according to whether the CXD1948R is used as DSSSTB or DSS-DVHS system digital I/F, as follows: A) DSS-STB system digital I/F: S_PacketSize: 090h; AddSize: 0h B) DSS-DVHS system digital I/F: S_PacketSize: 090h; AddSize: Ah The isochronous data format on the IEEE1394 bus does not change for A and B. Only the amount of data interfaced with the system changes. The DSS-STB system interfaces with 130 bytes as one packet of transport stream. The CXD1948R adds a 4-byte source packet header and 10 bytes of data set on the CFR via the host I/F to the received 130 bytes, then transmits them as an isochronous packet. For the DSS-DVHS system, only the source packet header is removed from the received isochronous packet, and 140 bytes of data are output as transport stream data. The above is for the case of transmission; in reception, 140 bytes of data is input from the DSS-DVHS system, and 130 bytes of data is output to the DSS-STB system. The same as for the DVB format, the amount of data transmitted in one isochronous cycle is set by the NOSP and NODB registers. Example of Interface with DSS System IEEE1394 Serial Bus DSS-STB system CXD1948R IEEE1394 Physical layer LSI IEEE1394 Physical layer LSI CXD1948R DSS-DVHS system S_PacketSize : 090H AddSize : Ah S_PacketSize : 090H AddSize : 0h Interface with DSS-STB system Isochronous packet on IEEE1394 bus 1394header headerCRC CIPheader1 CIPheader2 SPheader 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes Interface with DSS-DVHS system Additional Data 10 bytes Additional Data 10 bytes Payload Data 130 bytes Payload Data 130 bytes Payload Data 130 bytes Data_CRC 4 bytes - 25 - CXD1948R DSS/Isochronous Packet Structure (1 source packet) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1394Header data_length 0098h tag Header_CRC CIPHeader1 CIPHeader2 SPHeader 0 1 0 0 SID FMT 21h Reserved TIF Reserved channel reserved speed sy DBS 09h TF FN 10 QPC 000 FDF SPH reserved 1 DBC TimeStamp TimeStamp (27MHz) EF TF UF CR MS Reserved Reserved data0 data3 data4 data1 data5 Reserved Reserved data2 Channel Information Data (130 bytes) data126 data127 Data_CRC data128 data129 Note: The diagonally shaded areas ( ) for 1394Header and CIPHeader1 and 2 are attached automatically by the CXD1948R. Other areas are set from the external microcomputer via the host I/F. The white areas ( ) indicate additional data. In transmission from the CXD1948R to an IEEE 1394PHYIC, the four bits marked "reserved" and "speed" of the 1394Header are automatically replaced by "tcode". Additional Data Fields Field Name TIF TimeStamp EF TF UF CR MS Channel Information Reserved for bit rate - 26 - Time Stamp Invalid Flag Description 1: Invalid, 0: valid Time stamp value stamped at 27MHz synchronized to MPEG2 transport stream. Error Flag Transition Flag VBV Underflow Flag Copy Right Multi/Single 00: Single program, 01: 10: 11: Reserved 1: Error, 0: No Error 1: Transition (1sec), 0: No Transition 1: Underflow, 0: Normal CXD1948R 5-6. Relationship between Additional Data and CFR Registers The CXD1948R has 10 bytes of data registers for additional data. These are common registers for transmit and receive. Setting is done from the host I/F to add data to the transport stream data. For receive, the additional data is detected from the isochronous packet and the value is written in. The relationship between the CFR additional data registers AddData and the additional data in DSS format is described below. CFR Registers MSB AddData1 LSB MSB DSS Additional Data LSB TIF Reserved TimeStamp (27MHz) AddData2 AddData3 EF TF UF CR AddData4 AddData5 AddData6 MS Reserved Channel Infomation AddData7 AddData8 AddData9 Reserved AddData10 5-7. 27MHz Time Stamp When a 27MHz time stamp synchronized to the transport stream is added on the CXD1948R, the CFR 27MTS register is set to "1". Further, a 27MHz clock must be input from the CK27 pin. When the 27MTS register is set to "0", the 27MHz time stamp field value enters as is to the lowest 4 bits of the AddData1 register and the value of the AddData2 register. - 27 - CXD1948R 5-8. Dummy Packet Transmission The CXD1948R has a function that automatically transmits a dummy packet when isochronous transmission is muted, or when there is no packet to be transmitted during isochronous transmission. The dummy packet consists of header information only. The DBC value is the normal packet value transmitted on the next isochronous cycle. Dummy Packet Structure 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data_length 1394Header 0008h tag Header_CRC CIPHeader1 CIPHeader2 00 10 SID FMT Data_CRC DBS FN QPC FDF SPH reserved channel reserved speed sy DBC Note: The diagonally shaded areas ( ) for 1394Header and CIPHeader1 and 2 are attached automatically by the CXD1948R. Other areas are set from the external microcomputer via the host I/F. In transmission from the CXD1948R to an IEEE 1394PHYIC, the four bits marked "reserved" and "speed" of the 1394Header are automatically replaced by "tcode". Example of Dummy Packet Transmission (for transmit of 1 data block) IEEE1394 cycle DBC = 1 Isochronous packet DBC = 2 DBC = 2 DBC = 3 normal packet dummy packet - 28 - CXD1948R 5-9. Time Stamp The CXD1948R has a function that adds a time stamp to the input transport stream packet and transmits it, detects the time stamp on a received packet, and outputs the transport stream packet based on that value. The time stamp is 25 bits, and is superimposed on the source packet header. Source Packet Header Structure time stamp field 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CycleCount CycleOffset Time Stamp Field Field Name CycleCount CycleOffset Description Time intervals of less than 1 second are expressed in units of 125s. (0 to 1F3Fh) Time intervals of less than 125s are expressed in units of 24.576MHz clock cycles. (0 to BFF) Time Stamp Adding The CXD1948R takes in the internal cycle timer value when the transport stream packet is completely received. Next it adds the CFR TxDelay register value set from the host I/F to the cycle timer value, and superimposes it on the source packet header as a time stamp. Time Stamp Detection After completely receiving the isochronous packet, the CXD1948R detects the superimposed time stamp to the source packet header. It compares the detected time stamp value and the internal cycle timer value, and starts data output from the point where the times match. (Actually output request is performed.) Also, if the time is already past, it performs data output immediately. - 29 - CXD1948R Block Diagram CXD1948R (transmit side) IEEE1394 Serial BUS TxDelay host I/F CFR PACKETEN DETECT TimeStamp Cycle Timer MUX Isochronous FIFO transmit data IEEE1394 PHY LSI transport stream data CXD1948R (receive side) READREQ DETECT TimeStamp receive data Cycle Timer DEMUX Isochronous FIFO IEEE1394 PHY LSI transport stream data 5-10. Error Processing When a correct packet can not be received, for example if a CRC error is generated or a packet which violates protocol is received, the CXD1948R automatically performs error processing. Error processing control is done by setting the CFR ErrOutEn register. A description of error processing follows. Processing for Transmit ErrFlag input becomes valid when the CFR ErrBit Enable register is set to "1". The input error packet is processed in the same way as a normal packet. However, error information is also transmitted, so only the mode when additional data is added to the transport stream data is valid. (The superimposed position of the error information is the MSB of the additional data 3rd byte.) ErrFlag input becomes invalid when the ErrBitEnable register is set to "0". Processing for Receive ErrFlag output becomes valid when the CFR ErrBit Enable register is set to "1". When the received isochronous packet is judged as an error, ErrFlag is made "1" and output. Because the time stamp cannot be trusted, output is performed immediately. When the ErrFlagEnable register is set to "0", only the correctly received isochronous packets are output. - 30 - CXD1948R 5-11. Late Processing The CXD1948R automatically performs late processing when an isochronous packet is transmitted. In late processing, the time stamp superimposed on the source packet header of the packet for transmission is consulted, and if there is the possibility that the receiving side may not receive the entire packet within the timing indicated by the time stamp, the packet transmission is canceled. The time stamp value is the time when the transport stream packet was received plus TxDelay, so the number of packets for late processing can be reduced by making the TxDelay value larger. However, the upper limit of the TxDelay value depends on the stream transmission rate and the built-in FIFO buffer capacity. 6. Asynchronous Communication 6-1. Host/IF The host I/F controls data communication between the external CPU and the CXD1948R ATF/ARF/CFR/IPB1, respectively. Communications between the CPU and CXD1948R include: 1) CPU writes data to ATF asynchronous packet transmit 2) CPU reads data in ARF asynchronous packet receive 3) CPU writes data to CFR mode, header data setting 4) CPU reads data in CFR internal status, header data read-in 5) CXD1948R informs CPU of an interrupt event with an interrupt signal 6) CPU performs insert of isochronous packet from host I/F 7) CPU sets additional information (10 bytes) in isochronous packet The CXD1948R supports 16-bit and 8-bit host I/F. The ATF/ARF/CFR built in to the CXD1948R have a 32-bit structure, so all bits can not be accessed with one access. The target address must be accessed two consecutive times for 16 bits and four consecutive times for 8 bits. The roles played by the signals communicated between the CXD1948R and the external microcomputer are given bellow. DATA [15:0] ADDRESS [7:0] in/out in Data for writing to or reading from specified address Address for writing or reading data Data destination (CFR or FIFO) and data breakpoint (Write or Confirm) are discriminated according to the address Access enable from host bus (low active) Data read/write enable signal (high: read; low: write) Indicates access (read or write) completed to specified address (low active) Interrupt signal. Indicates some kind of interrupt when low Type of interrupt and mask specified by CFR Host I/F data bus switching H: 16 bits; L: 8 bits XCS XW/R XWAIT XINT X8/16 in in out out in 1 ATF (Asynchronous Transmit Fifo), ARF (Asynchronous Receive Fifo), CFR (Configuration Register), IPB (Insert Packet transmit Buffer) - 31 - CXD1948R Writing Timing to ATF/CFR/IPF For write, the CXD1948R latches ADDRESS, XW/R and DATA at XCS falling edge. The timing chart is illustrated below. Tcyc Tsu1 XCS Th1 Tcych ADDRESS XW/R Tsu2 DATA Valid XWAIT Th2 Twait Th3 Tsu1 0ns, Tsu2 5ns, Th1 0ns Tcyc 250ns, Tcych 100ns, Twait 100ns, Th2 5ns, Th3 5ns Timing for Data Read from ARF/CFR For read, the CXD1948R latches ADDRESS and XW/R at XCS falling edge. The timing chart is illustrated below. Tcyc Tsu XCS Tcych ADDRESS XW/R DATA invalid Th1 valid Th2 XWAIT Th3 Twait Th4 Tsu 0ns, Th1 5ns Tcyc 400ns, Tcych 100ns, Twait 250ns, Th2 5ns, Th3 5ns, Th4 5ns - 32 - CXD1948R Configuration Register (CFR) Address Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 04 RxSld idVal Version CyMas Power Status root Revision NodeNumber RstRx RstTx Version CFMContID IFEmpty IFEmpty ErrOutEn IPktLate IPktLate TmsDis IPTxGo StrSid IsAbFail IsAbFail AckCtl IRxC BusNumber RxEn TxEn NodeSum AsyncAI CySec CyMasEn CyTEn ITxC Node Address Control Interrupt Interrupt Mask Cycle Timer DIF Mode 08 0C 10 14 BsyCtrl FairGap FairGap BusRst PhRRx BlkBusDep ATRC HdrErr ATStk TCErr SntRj AIDT16 CyAbFail CyAbFail CmdRst CmdRst RxLack RxLack TxRdy CyDne RxDta CyPnd TxLate EndSlf PhyInt BusRst PhRRx CySec TxRdy CyDne CyPnd RxDta CyLst TxLate EndSlf HdrErr PhyInt ATStk TCErr CycleNumber IGFMode HSRxOn HSTxOn ErrBitEn IFClear IGFOn 27MTS LPS SntRj 18 1C RxChannel TxDelay PacketBanks S_PacketSize DiffGap CyLst CycleOffset IFFull IFOvf ITStk CySt Int IFFull IFOvf ITStk CySt Int IsoTxRx Init Diagnostics Async Status Phy Chip Access PDATA1 PDATA0 ArfDc FrGp Arf AEmpty regRW ArbGp EnSp 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 SIGapCnt ATAck ArfEmpty WrPhy ArfAFull Arf 4There AtfEmpty AtfAFull Atf 4Avail Atf AEmpty ArfFull AtfFull RdPhy PhyRegAd PhyRegData PDIR4 Clear ATF Clear ARF PhyAdRxReg PDIR1 PDIR3 PDIR2 PDIR0 PhyDataRxReg PDATA3 PDATA4 PDATA2 Parallel Port Tx1394Hdr TxCIPHdr1 TxCIPHdr2 NOSP { 0, 0 } NODB Tx1394Hdr {Tag [1: 0] , ChNumber [5: 0] , 1394Rsv [1: 0 ] , Speed [1: 0 ] , sy [3 :0] } TxCIPHdr1 { DBS [7: 0], FN [1: 0], QPC [2: 0], SPH, rsv [1: 0] } TxCIPHdr2 { 1, 0, FMT [5 : 0], TF, FDF [22 : 0] } 27MTIF 27Mrsv SPH-reserved AddData6 AddData10 AddSize AddData5 AddData9 AddData2 AddData4 AddData8 AddData1 AddData3 AddData7 Rx1394Hdr Rx1394Hdr sy [3 : 0] SPH-rsv/AddData1-2 AddData3-6 AddData7-10 Rx1394Hdr RxCIPHdr1 RxCIPHdr2 Rx1394Hdr Data_length [15 : 0] , Tag [1 : 0] , ChNumber [5 : 0] tCode [3 : 0] RxCIPHdr1 EOH, form, SID [5 : 0] , DBS [7 : 0] , FN [1 : 0] , QPC [2 : 0] , SPH, rsv [1 : 0] , DBC [7 : 0] RxCIPHdr2 EOH, form, TF, FMT [5 : 0] , FDF [22 : 0] 64 68 6C 70 74 78 7C Note: The shaded areas ( IPB Write (first quadlet of the packet) IPB Write IPB Write (confirm write) ATF Write (first quadlet of the packet) ATF Write/ARF Read ATF Write (confirm write) ) are reserved and can not be used. - 33 - CXD1948R 6-2. CFR (Configuration Register) This is a memory space to store the status information and operation mode and packet header information inside the chip. Read/write with the external microcomputer can be performed via the host I/F. (Be sure to set to "0" when writing to the reserved area.) The address map and register contents are shown below. Register Description 1) Version/Revision Register These registers have the CXD1948R version/revision written in them. The register address is 00h; they are read only, and the initial value is 0000_0001h. Bit 31 to 16 15 to 0 Name Version Revision CXD1948R Version Number CXD1948R Revision Number Function 2) Node Address Register These registers are used for packet receive/refuse control, and to monitor root/cycle master status and the total number of nodes connected. The register address is 04h and the initial value is FFFF_0040h. Only the bus number is read/write, and the other registers are normally read only, but the diagnostic register can be read/write by setting regRW to "1". Bit 31 to 22 21 to 16 15 14 12 11 to 6 Name Bus Number Node Number root Power Status CyMst NodeSum Bus number of connected bus Node number of this link Root/not root for this link 1: root; 0: not root Cable power status for this mode Whether or not this link is cycle master 1: cycle master; 0: not Total number of connected nodes. Value is 0 when an error occurs in Self_ID communication. The Phy_ID of the contender is inserted here. However, when the node can itself be a contender and it has a larger Phy_ID than this value, then the node itself is the contender. Function 5 to 0 CFMcontID - 34 - CXD1948R 3) Control Register These registers perform settings for the CXD1948R basic operations. The register address is 08h; they are read/write, and the initial value is C400_0A00h. Bit 31 30 Name idVal RxSld Function Receives packet from the address set in the node address register at "1". Receives packet at bus number "3Fh" node number "3fh" only at "0". Validates reception of SelfID packet at "1". Non-valid at "0". Processing for NodeSum, CFMContID, DiffGap and SIGapCnt is invalid. Controls Busy status of input packet. 000 = Returns busy according to normal busy/retry protocol when necessary. (Always fixed at "000" on the CXD1948R) Transmitter does not transmit Arbitration and packet when "0" Receiver does not receive packet when "0" Sync resets transmitter when set to "1" This bit is cleared automatically Sync resets receiver when set to "1" This bit is cleared automatically Access limits on Broadcast packets for the CSR bus-dependent area can be set here. Each bit corresponds to 128 bytes of the CSR bus-dependent area. With the LSB corresponding to the first 128 bytes, and so on until the MSB corresponding to the last 128 bytes, access to any area for which the corresponding bit has been set "1" is invalid. The Retry Code can be controlled. The Retry Code for the packet being sent is the logical OR of the value set here and the value stored in ATF. Selects AIDT bus width. 8 bits at "0" and 16 bits at "1" Transport stream I/F setting. Synchronous at "0" and asynchronous at "1". When "1" and the node becomes the ROOT, Cycle Master functions are activated. Validates Cycle Offset increment at "1" Transmits isochronous packet with tCode = C at "1" Transmits isochronous packet with tCode = A at "0" Receives tCode = A, tCode = C packets as isochronous packet at "1" Receives tCode = A packet as isochronous packet at "0" Controls Ack code which is returned when tCode = 0, 1 (Write request quadlet/block) packets are received. 0: Ack code = 1 (complate), 1: Ack code = 0 (pending) Does not use time stamp for data read during receive at "1" Uses time stamp for data read during receive at "0" Takes received SelfID packet in to ARF at "1" Does not take received SelfID packet in to ARF at "0" Outputs error packet at ErrFlag High during receive at "1" Does not output error packet during receive at "0" Transmits insert packet at "1" Automatically changes to "0" after transmit 29 to 27 26 25 21 20 BsyCtrl TxEn RxEn RstTx RstRx 19 to 16 BlkBusDep 15, 14 13 12 11 9 7 6 ATRC AIDT16 AsyncAI CyMasEn CyTEn ITxC IRxC 0 AckCtl 5 3 2 1 TmsDis StrSid ErrOutEn IPTxGo - 35 - CXD1948R 4) Interrupt and Interrupt-Mask Registers These registers combine the Interrupt Register, which informs the host I/F of changes in the CXD1948R status, and the Interrupt Mask Register, which masks the Interrupt Register. The address of the Interrupt Register is 0Ch, and when the regRW bit is "0", bits other than Int bit are cleared by writing. When the regRW bit is "1" all bits are read/write. The address of the Interrupt-Mask Register is 10H and it is read/write. The initial value for both registers is 0000_0000h. Bit 31 30 29 28 27 26 25 24 23 20 19 17 16 15 12 11 10 9 8 7 6 5 4 3 2 1 0 Int PhyInt PhRRx BusRst FairGap TxRdy RxDta CmdRst EndSlf ITStk ATStk SntRj HdrErr TCErr IFOvf CySec CySt CyDne CyPnd CyLst CyAbFail IPktLate TxLate RxLack IFEmpty IFFull IsAbFail Name Function Indicates the OR result of all the interrupt (interrupt mask) bits. Indicates Phy Interrupt received from Phy chip Indicates data received from Phy to Phy register Indicates Bus Reset received from Phy Indicates FairGap received from Phy Transmitter is able to transmit Receiver has received a correct packet Receiver has received a packet addressed to CSR RESET_START register SelfID phase complete Transmitter detected wrong data in isochronous FIFO during isochronous transmit Transmitter detected wrong data in asynchronous FIFO during asynchronous transmit Receiver transmitted Busy Ack for a packet transmitted to this node because receive FIFO is full Receiver detected Header CRC error in the packet transmitted to this node Transmitter detected wrong tCode data in transmit FIFO Indicates overflow in isochronous FIFO Indicates that Cycle Timer register Cycle Number upper 7 bits were incremented. (This is generated almost every second when Cycle Timer is valid.) Transmitter/Receiver transmitted/received Cycle Start packet After transmit or receive of Cycle Start packet, FairGap was detected on the bus. This means that the isochronous cycle is complete. Indicates that Cycle Timer register Cycle Offset is "0". Stays as is until isochronous cycle is complete. When not Cycle Master, indicates that Cycle Timer completed 2 cycles without receiving Cycle Start packet. Failure of Cycle Start packet transmission Arbitration Late transmit of insert packet Late transmit of isochronous packet Indicates isochronous packet non-continuous DBC Isochronous FIFO empty Isochronous FIFO full Failure of isochronous packet transmission Arbitration - 36 - CXD1948R 5) Cycle Timer Registers These registers are composed of the 24.576MHz clock cycle Cycle Offset and the 125s in its host, and the Cycle Master that counts 1 second. The value of all nodes are regulated by the Cycle Master node. The register address is 14h; it is read/write, and the initial value is 0000_0000h. Bit 31 to 12 Name CycleNumber Function The upper 7 bits counts seconds (1Hz) and the lower 13 bits count the isochronous cycle (8kHz = 125s). The values are controlled by Control register Cycle Master and Cycle Timer Enable. Counts the system clock (24.576MHz). The Cycle Number is incremented when this counter completes one cycle. The value is controlled by Control register Cycle Master and Cycle Timer Enable. 11 to 0 CycleOffset 6) DIF Mode Register This register performs settings for transmit and receive of isochronous packets, and sets transmitted isochronous packet 1394 header information (specified in the Draft). The register address is 18h; it is read/write, and the initial value is 0100_0000h. Bit 31 30 29 28 27 26 25 24 23 to 16 Name IGFOn IGFMode HSTxOn HSRxOn IFClear ErrBitEn 27MTS LPS RxChannel Function Isochronous FIFO operation is active at "1" Changes isochronous FIFO operation to transmit at "1". Receives at "0" Isochronous transmit side operation is active at "1". Invalid at "0" Isochronous receive side operation is active at "1". Invalid at "0" Clears isochronous FIFO at "1" Uses 27MHz time stamp at "1" Does not use 27MHz time stamp at "0" LPS pin high at "1" LPS pin low at "0" Tag/Channel Number for isochronous packet receive 7) IsoTxRx Init This register performs setting related to isochronous packet transmit/receive time stamp, and packet size and packet bank. The register address is 1Ch; it is read/write, and the initial value is 0000_0000h. Bit 26 to 16 13 to 9 8 to 0 Name TxDelay PacketBanks S_PacketSize Function Transmission delay time for isochronous packets. The upper 6 bits are added to the lower 6 bits of the Cycle Number, and the lower 5 bits are added to the upper 5 bits of the Cycle Offset to obtain the time stamp. Sets number of isochronous FIFO packet bank Sets isochronous packet source packet size The value includes SPH and additional data (byte units) - 37 - CXD1948R 8) Diagnostic Register This register controls or monitors the CXD1948R status. The register address is 20h and the initial value is 0000_0000h. Only the EnSp bit and regRW bit are read/write; other bits are read/write when the regRW bit is "1" and read only when it is "0". Bit 31 29 28 27 6 5 to 0 Name EnSp ArbGp FrGp regRW DiffGap SIGapCnt Function Receives all packets on the bus regardless of receiver address and format at "1". Invalid at "0". Bus is in idle state due to Arbitration Reset Gap Bus is in idle state due to Fair Gap Almost all registers are read/write when set at "1" "1" when there is dispersion in Gap count values in received Self ID This value is entered when all Gap count values in received Self ID are the same. "00h" when bus reset is generated. 9) Asynchronous Transmit and Receive FIFO Status Registers These registers can monitor and control the ATF/ARF statuses. The register address is 24h and the initial value is 0428_0000h. Only the ClearATF bit and ClearARF bit are read/write; other bits are read/write when the regRW bit is "1" and read only when it is "0". Bit 31 30 29 28 27 26 23 22 21 20 19 15 13 3 to 0 Name ARFFull ARFAFull ARF4Th ARFDc ARFAEmpty ARFEmpty ATFFull ATFAFull ATF4Avail ATFAEmpty ATFEmpty ClearATF ClearARF ATAck Function ARF is full when "1" and receive is not possible ARF can receive only one more quadlet when "1" More than 4 quadlets of data are written in ARF when "1" This is the control bit for reading a packet from ARF, and is "1" only when the first and last quadlets of the packet are read. Only one more quadlet of data is written in ARF when "1" ARF is empty when "1" and there is no data to be read ATF is full when "1" and write is not possible ATF can write only one more quadlet when "1" More than 4 quadlets of data can be written in ATF when "1" ATF has only one more quadlet of data not transmitted when "1" ATF is empty when "1" and there is no data for transmit Sync reset of ATF when "1" (Self Clear) Sync reset of ARF when "1" (Self Clear) Value of received Ack code - 38 - CXD1948R 10) Phy Chip Access Registers These registers are used for read/write of the contents of the Phy chip Phy register connected to the CXD1948R. The register address is 28h and the initial value is 0000_0000h. Bit 31 30 27 to 24 23 to 16 11 to 8 7 to 0 Name RdPhy WrPhy PhyRegAd PhyRegData PhyAdRxReg Function The CXD1948R requests read to the address set in PhyRegAd via the Phy I/F when "1" The CXD1948R requests write to the address set in PhyRegAd via the Phy I/F when "1" Sets the read/write address of the connected Phy chip Phy register Value of data for write to address specified by PhyRegAd Value of read Phy register address during read PhyDataRxReg Value of the read Phy register data during read 11) Tx1394Hdr Registers These registers are used to set the value of 1394Hdr added at the CXD1948R during isochronous transmit, and the number of data blocks transmitted in the isochronous cycle. The register address is 30h and the initial value is 0000_0000h. Bit 31 to 28 26 to 24 Name NOSP NODB Function Sets number of source packets transmitted in the isochronous cycle Sets number of data blocks transmitted in the isochronous cycle Header when transmitting isochronous packet bit15 to bit14: Tag [1 : 0], Isochronous data format tag bit13 to bit8: ChNumber [5 : 0], Isochronous Channel bit7 to bit6: Rsv [1 : 0], Reserved bit5 to bit4: Speed [1 : 0], Speed code bit3 to bit0: Sy [3 : 0], Synchronization Code 15 to 0 Tx1394Hdr 12) TxCIPHdr1 Registers These registers are used to set the value of CIPHdr1 added at the CXD1948R during isochronous transmission and settings related to the 27MHz time stamp. CIPHdr1 is one of the CIP headers. The register address is 34h and the initial value is 0000_0070h. Bit Name Function Value of CIPHdr1 added during isochronous transmit bit31 to bit30: "00" bit23 to bit16: DBS, one data block size (quadlet) bit15 to bit14: FN [1 : 0], Franction number bit13 to bit11: QPC [2 : 0], Quadlet padding Count bit10: SPH, Source packet Header bit9 to bit8: rsv [1 : 0] reserved 27MHz time stamp value invalid at "1" 27MHz time stamp value valid at "0" Reserve area when 27MHz time stamp is used 23 to 8 TxCIPHdr1 7 6 to 4 27MTIF 27Mrsv - 39 - CXD1948R 13) TxCIPHdr2 Registers These registers are used to set the value of CIPHdr2 added at the CXD1948R during isochronous transmission. CIPHdr2 is one of the CIP headers. The register address is 38h and the initial value is 0000_0000h. Bit Name Function Value of CIPHdr2 added during isochronous transmit bit31 to bit30: "10" bit29 to bit24: FMT [5 : 0], Format ID bit23: TF, Time Shift 1: TimeShift 0: no TimeShift bit22 to bit0: Format Dependet Field 31 to 16 TxCIPHdr2 14) SPH-reserved/AddData1, 2 Registers These registers are used for setting the reserve value of the source packet header added/detected by the CXD1948R during isochronous communication, and for setting and storing additional data and setting the number of additional data. The register address is 3Ch and the initial value is 0000_0000h. Bit 31 to 25 19 to 16 15 to 8 7 to 0 Name SPH-reserved AddSize AddData1 AddData2 Function Value of source packet header reserve stored during receive or added during isochronous communication Sets number of data added during isochronous transmission Value of data 1 stored during receive or added during isochronous communication Value of data 2 stored during receive or added during isochronous communication 15) AddData3 to 6 Registers These registers are used for the data added/detected by the CXD1948R during isochronous communication. The register address is 40h and the initial value is 0000_0000h. Bit 31 to 24 23 to 16 15 to 8 7 to 0 Name AddData3 AddData4 AddData5 AddData6 Function Value of data 3 stored during receive or added during isochronous communication Value of data 4 stored during receive or added during isochronous communication Value of data 5 stored during receive or added during isochronous communication Value of data 6 stored during receive or added during isochronous communication 16) AddData7 to 10 Registers These registers are used for the data added/detected by the CXD1948R during isochronous communication. The register address is 44h and the initial value is 0000_0000h. Bit 31 to 24 23 to 16 15 to 8 7 to 0 Name AddData7 AddData8 AddData9 AddData10 Function Value of data 7 stored during receive or added during isochronous communication Value of data 8 stored during receive or added during isochronous communication Value of data 9 stored during receive or added during isochronous communication Value of data 10 stored during receive or added during isochronous communication - 40 - CXD1948R 17) Rx1394Hdr Registers These registers are used to store the value of the 1394Hdr detected by the CXD1948R during isochronous receive. The register address is 48h and the initial value is 0000_0000h. Bit Name Function Value of 1394Hdr detected during isochronous receive bit31 to bit16: Data_length [15 : 0], 1 isochronous packet byte length bit15, bit14: Tag [1 : 0], Isochronous data format tage bit13 to bit8: ChNumber [5 : 0], Isochronous channel Number bit7 to bit4: tCode [3 : 0], Isochronous Transaction code bit3 to bit0: sy [3 : 0] Synchronization Code 31 to 8 3 to 0 Rx1394Hdr 18) RxCIPHdr1 Registers These registers are used to store the value of the CIPHdr1 detected by the CXD1948R during isochronous receive. The register address is 4Ch and the initial value is 0000_0000h. Bit Name Function Value of CIPHdr1 detected during isochronous receive bit31: EOH bit30: form bit29 to bit24: SID, Source [5 : 0] Node ID bit23 to bit16: DBS [7 : 0], Data Block Size bit15, bit14: FN [1 : 0] Fraction bit13 to bit11: QPC [2 : 0], Quadlet Padding Count bit10: SPH, Source Packet Header bit9, bit8: rsv [1 : 0], Reserved bit7 to bit0: DBC [7 : 0], Data Block Counter 31 to 0 RxCIPHdr1 19) RxCIPHdr2 Registers These registers are used to store the value of the CIPHdr2 detected by the CXD1948R during isochronous receive. The register address is 50h and the initial value is 0000_0000h. Bit Name Function Value of CIPHdr2 detected during isochronous receive bit31: EOH bit30: form bit29 to bit24: FMT [5 : 0], Format ID bit23: TF, TimeShift Flag bit22 to bit0: FDF [22 : 0], Format Dependent on Fields 31 to 0 RxCIPHdr2 20) IPBWrite (first quadlet of the packet) Registers The first quadlet of the transmitted insert packet is written in these registers. The register address is 64h and the initial value is 0000_0000h. Bit 31 to 0 Name IPBWrite (first quadlet of the packet) Function Writes the first quadlet of the transmitted insert packet. - 41 - CXD1948R 21) IPBWrite Registers The second through the next to the last quadlets of the transmitted insert packet are written in these registers. The register address is 68h and the initial value is 0000_0000h. Bit 31 to 0 Name IPBWrite Function Writes the second through the next to the last quadlets of the transmitted insert packet. 22) IPBWrite (confirm write) Registers The last quadlet of the transmitted insert packet is written in these registers. The register address is 6Ch and the initial value is 0000_0000h. Bit 31 to 0 Name IPBWrite (confirm write) Function Writes the last quadlet of the transmitted insert packet. 23) ATFWrite (first quadlet of the packet) Registers The first quadlet of the transmitted asynchronous packet is written in these registers. The register address is 70h and the initial value is 0000_0000h. Bit 31 to 0 Name ATFWrite (first quadlet of the packet) Function Writes the first quadlet of the transmitted asynchronous packet. 24) ATFWrite/ARFRead Registers The second through the next to the last quadlets of the transmitted asynchronous packet are written in these registers. Also, the asynchronous packet read from the ARF during receive is read one quadlet at a time. The register address is 74h and the initial value is 0000_0000h. Bit 31 to 0 Name ATFWrite /ARFRead Function Transmit: Writes the second through the next to the last quadlets of the transmitted asynchronous packet. Receive: Writes the asynchronous packet read from ARF one quadlet at a time. 25) ARFWrite (confirm write) Registers The last quadlet of the transmitted asynchronous packet is written in these registers. The register address is 7Ch and the initial value is 0000_0000h. Bit 31 to 0 Name ATFWrite (confirm write) Function Writes the last quadlet of the transmitted asynchronous packet. - 42 - CXD1948R 26) Parallel Port Registers These registers are used to set the parallel port I/O direction and data. The register address is 2Ch and the initial value is 0000_0000h. Be sure to set all non-pertinent registers to "0". Bit 12 11 10 9 8 4 3 2 1 0 Name PDIR4 PDIR3 PDIR2 PDIR1 PDIR0 PDATA4 PDATA3 PDATA2 PDATA1 PDATA0 PORT4 I/O switching setting. PORT3 I/O switching setting. PORT2 I/O switching setting. PORT1 I/O switching setting. PORT0 I/O switching setting. Function 0: Input, 1: Output 0: Input, 1: Output 0: Input, 1: Output 0: Input, 1: Output 0: Input, 1: Output Sets the PORT4 output data when PDIR4 is 0. Inputs the PORT4 input data when PDIR4 is 1. Sets the PORT3 output data when PDIR3 is 0. Inputs the PORT3 input data when PDIR3 is 1. Sets the PORT2 output data when PDIR2 is 0. Inputs the PORT2 input data when PDIR2 is 1. Sets the PORT1 output data when PDIR1 is 0. Inputs the PORT1 input data when PDIR1 is 1. Sets the PORT0 output data when PDIR0 is 0. Inputs the PORT0 input data when PDIR0 is 1. - 43 - CXD1948R 6-3. Asynchronous Packet Transmission Packet data is written from the external microcomputer to the ATF inside the CXD1948R in order to transmit an asynchronous packet. At this time the first quadlet of the packet only is written in the CFR ATFWrite (first quadlet of the packet) register (70h). The second through the next to the last quadlets are written in the CFR ATFWrite/ARFRread registers (74h). Then the last quadlet is written in the CFR ATFWrite (confirm write) register (7Ch) and the packet is stored in the ATF. However, if the ATF is full, write will not actually be performed even when write is executed. Once the bus is enabled, transmit takes place automatically. The procedure for transmitting a quadlet write request packet is given here as an example. (for 8-bit data interface) (1) Confirming that ATF is not full The CFR Async Status register (24h to 27h) is read to confirm that the 23rd bit (AtfFull bit) is low. If it is high it means that there are some unsent packets stored and it waits until they are transmitted. XCS ADDRESS 24h 25h 26h 27h XW/R DATA 28h This indicates that ATF is empty. It is "80h" when ATF is full. The number of quadlets that can be stored in ATF can be found from the value of the Async Status register bits [23 : 19]. The following six states can be found, so a judgement must be made as to whether write is possible from the number of quadlets in the packet being sent from the external microcomputer. AtfFull = High: AtfAFull = High: All bits low: Atf4Avail = High: Atf4Avail = High, AtfAEmpty = High: Atf4Avail = High, AtfEmpty = High: Can't write only 1 quadlet 2 to 3 quadlet 4 to 28 quadlet 29 quadlet 30 quadlet - 44 - CXD1948R (2) First quadlet of the transmitted packet Write Let the first quadlet of the quadlet write request packet be "00000000h". This is written in the CFR ATFWrite (first quadlet of the packet) register. XCS ADDRESS 70h 71h 72h 73h XW/R DATA 00h 00h 00h 00h (3) Second quadlet of the transmitted packet Write Let the second quadlet of the quadlet write request packet be "FFC1FFFFh". This is written in the CFR ATFWrite/ARFRead register. XCS ADDRESS 74h 75h 76h 77h XW/R DATA FFh FF C1 FFh (4) Third quadlet of the transmitted packet Write Let the third quadlet of the quadlet write request packet be "F000000Ch". This is written in the CFR ATFWrite/ARFRead register. XCS ADDRESS 74h 75h 76h 77h XW/R DATA 0Ch 00h 00h F0h - 45 - CXD1948R (5) Last quadlet of the transmitted packet Write Let the last quadlet of the quadlet write request packet be "12345678h". This is written in the CFR ATFWrite (confirm write) register. XCS ADDRESS 7Ch 7Dh 7Eh 7Fh XW/R DATA 78h 56h 34h 12h The quadlet write request packet is stored in the ATF as shown above. When the bus is enabled, the CXD1948R transmits automatically. If transmit does not take place, the CFR interrupt register (0Ch to 0Fh) must be read to confirm if the ATStk bit or TCErr bit is high. If these bits are high, the packet stored in the ATF may not be correct. ATStk = High: If the first quadlet of the packet was not written in the CFR ATFWrite (first quadlet of the packet) register but was written in the ATFWrite/ARFRead register or the ATFWrite (confirm write) register. TCErr = High: A value that is not a transaction code able to be transmitted by asynchronous packet is written in the tCode field of the first quadlet of the packet. The transactions codes that can be transmitted as asynchronous packets are any of (0, 1, 2, 4, 5, 6, 7, 9, B, Eh). For either of ATStk or TCErr above, the next packet for write will not be transmitted even if it is correct. At this time "1" must be written in the Async Status register ClearATF bit in order to clear the ATF. Transmit is then enabled when a correct packet is written. - 46 - CXD1948R 6-4. Asynchronous Packet Reception Basically, if there is room to write the packet in FIFO and the destination_ID matches, then asynchronous packets are received. Receive is completed when the packet data is read from the ARF inside the CXD1948R by the external microcomputer. The CXD1948R raises an RxDta flag when a packet is received. (Normally, if the RxDta bit of the CFR Interrupt Mask register (10h to 14h) is set at "1", XINT goes low when a packet is received and this can be detected.) Next, the CFR Async Status register (24h to 28h) ArfEmpty bit should be low. This indicates that a correct packet was received. After this, one quadlet at a time can be read by reading the CFR ATFWrite/ARFRead registers (74h to 78h). Packet receive is completed by repeating this until the ArfEmpty bit goes high. However, if the ARF status is empty, read will not be done even if Read is executed. In this case, the data read by the microcomputer will be the previously read value. The procedure for receiving a quadlet write request packet is given here as an example. (for 8-bit data interface) (1) Confirming that the packet was received The CFR Interrupt register (0Ch to 0Fh) is read to confirm that the 25th bit (RxDta bit) is high. XCS ADDRESS 0Ch 0Dh 0Eh 0Fh XW/R DATA 82h This indicates that RxDta only was generated. (2) Confirming that the received packet was stored correctly in FIFO The CFR Async Status register (24h to 27h) is read to confirm that the 26th bit (ArfEmpty bit) is low. If this bit is high it means that reception may be in progress (all quadlets have not arrived). Read can not be done in this state, so wait and then clear again. - 47 - CXD1948R XCS ADDRESS 24h 25h 26h 27h XW/R DATA 20h This indicates ARF4There flags up. In the above example, the Arf4There are high and ArfEmpty is low. This means that the packet stored in FIFO has more than 4 quadlets, including the footer (quadlet to which the Link that received the packet is added automatically; speed and ackSent, etc. are written). ArfDc is "1" only when the read quadlet is a start quadlet or a footer of packet. The read quadlet can be identified whether it is a start quadlet or a footer by confirming the ArfDc bit of the Async Status register (24h to 27h) after reading the qualet. (3) First quadlet of the received packet Read The CFR ATFWrite/ARFRead register is read. XCS ADDRESS 74h 75h 76h 77h XW/R DATA 00h 00h C0h FFh The data read is "FFC00000h". The read quadlet can be identified as a start quadlet by confirming the ArfDc bit of the Async Status register (24h to 27h) after reading the qualet. - 48 - CXD1948R (4) Second quadlet of the received packet Read The CFR ATFWrite/ARFRead register is read. As in (2) before, when the status is read after this read, the ArfDc bit should be low. XCS ADDRESS 74h 75h 76h 77h XW/R DATA FFh FFh C1h FFh (5) Third quadlet of the received packet Read The CFR ATFWrite/ARFRead register is read. XCS ADDRESS 74h 75h 76h 77h XW/R DATA 20h 02h 00h F0h The data read is "F0000220h". (6) Fourth quadlet of the received packet Read The CFR ATFWrite/ARFRead register is read. XCS ADDRESS 74h 75h 76h 77h XW/R DATA 78h 56h 34h 12h The data read is "12345678h". - 49 - CXD1948R (7) Checking for remaining packets still in FIFO 4 quadlets were read in preceding items (1) to (6). They were read continuously because Arf4There was high. If Arf4There was low, Async Status must be read after 1 quadlet is read, to find out if ArfEmpty is high. Even if Arf4There is high, as in this case, after the 4th quadlet read must be done while checking ArfEmpty in the same way. XCS ADDRESS 24h 25h 26h 27h XW/R DATA 08h This indicates that the ARF Dc flag is up, and ARF is AlmostEmpty. In the above example the Arf4There bit is low, so a maximum of 3 more quadlets can be predicted, but the ArfAEmpty bit is high, so there is only one more quadlet in FIFO. Therefore, the probability is high where the quadlet to be read next is a footer. (8) Fifth quadlet of the received packet Read The CFR ATFWrite/ARFRead register is read. XCS ADDRESS 74h 75h 76h 77h XW/R DATA 01h 00h 00h 00h The data read is "00000001h". The lower 4 bits of this quadlet are the ackSent field, and this indicates "01h" transmitted as this packet's Ack_code. This is always written even if the packet is one which does not have Ack_code transmitted, such as a broadcast packet. If this value is "04h", the ARF may have become full during receive and quadlets may be missing. If it is "0Dh", an error was detected in the data field CRC check of the received packet, or data_length and the actual data length do not match. - 50 - CXD1948R (9) Checking for remaining packets still in FIFO The last quadlet was read in (8) before, so there should be no more packets in FIFO. In addition, it is confirmed whether the quadlet read last is a footer at the same time. XCS ADDRESS 24h 25h 26h 27h XW/R DATA 14h This indicates that ARF Dc flag is up, and ARF are Empty. As seen above, it can be confirmed that ARF is Empty and the quadlet read last is a footer. This completes asynchronous packet reception. - 51 - CXD1948R 6-5. CXD1948R Data Format 6-5-1. Asynchronous Transmit (Host Bus ( CXD1948R) The following are the four basic formats for asynchronous data during transmit. a) No-data Packets (Used for quadlet read requests and all write responses.) b) Quadlet Packets (Used for quadlet write requests, quadlet read request and block read responses.) c) Block Packets (Used for lock requests, lock responses, block write requests and block read responses.) d) Unformatted data 6-5-1-1. No-data Transmit The data format for no-data transmit is shown below. The 1st quadlet contains packet control information. The 2nd and 3rd quadlets contain 16-bit Destination ID and 48-bit Destination Offset for request, or Response Code for response. Quadlet Read Request Transmit Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 imm spd tLabel rt tCode priority destinationID destinationOffsetLow destinationOffsetHigh Write Response Transmit Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 imm spd tLabel rCode rt tCode priority destinationID No-data Transmit Fields Field Name imm spd tLabel rt tCode priority destinationID Description Immediately tries to transmit continuously after Acknowledge is sent, if "1" is set (Used for Phy Read and Lock Response.) Transmit speed 00: 100Mbps; 01: 200Mbps; 10: 400Mbps; 11: Reserved Transaction Label. Used as a pair with response packet relative to request packet. This packet's Retry Code 00: New; 01: Retry-X, 10: Retry-A, 11: Retry-B This packet's Transaction Code This packet's Priority Level For values other than "0", the transmitter uses Priority Arbitration relative to this packet Indicates this packet's Destination bus number in 10 bits and the Node number in 6 bits destinationOffsetHigh, Two continuous such areas indicate Destination Node address space address. This destinationOffsetLow address must be in quadlet units. rCode Response Code for write response packet - 52 - CXD1948R 6-5-1-2. Quadlet Transmit The data format for quadlet transmit is shown below. The 1st quadlet contains packet control information. The 2nd and 3rd quadlets contain 16-bit Destination ID and 48-bit Destination Offset for request, or Response Code for response. The 4th quadlet is quadlet data for Read responses and Write Quadlet requests. It is Data Length and Reserved for Block Read request. Quadlet Write Request Transmit Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 imm spd tLabel rt tCode priority destinationID destinationOffsetLow quadlet data destinationOffsetHigh Quadlet Read Response Transmit Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 imm spd tLabel rCode rt tCode priority destinationID quadlet data Block Read Request Transmit Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 imm spd tLabel rt tCode priority destinationID destinationOffsetLow dataLength destinationOffsetHigh - 53 - CXD1948R Quadlet Transmit Fields Field Name imm spd tLabel rt tCode priority destinationID Description Immediately tries to transmit continuously after Acknowledge is sent, if "1" is set (Used for Phy Read and Lock Response.) Transmit speed 00: 100Mbps; 01: 200Mbps; 10: 400Mbps; 11: Reserved Transaction Label. Used as a pair with response packet relative to request packet. This packet's Retry Code 00: New; 01: Retry-X, 10: Retry-A, 11: Retry-B This packet's Transaction Code This packet's Priority Level For values other than "0", the transmitter uses Priority Arbitration relative to this packet Indicates this packet's Destination bus number in 10 bits and the Node number in 6 bits destinationOffsetHigh, Two continuous such areas indicate Destination Node address space address. destinationOffsetLow This address must be in quadlet units. quadlet data rCode dataLength Writes transmit data for Quadlet Write requests and Quadlet Read response Response Code for Quadlet Response packet Writes how many bytes requested for Block Read request - 54 - CXD1948R 6-5-1-3. Block Transmit The data format for block transmit is shown below. The 1st quadlet contains packet control information. The 2nd and 3rd quadlets contain 16-bit Destination ID and 48-bit Destination Offset for request, or Response Code for response. The 4th quadlet contains data length and Extended Transaction Code (all "0" except for Lock Transaction). Block Transmit Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 imm spd tLabel rt tCode priority destinationID destinationOffsetLow dataLength destinationOffsetHigh extendedTcode black data Block Read or Lock Transmit Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 imm spd tLabel rCode rt tCode priority destinationID dataLength extendedTcode black data - 55 - CXD1948R Block Transmit Fields Field Name imm spd tLabel rt tCode priority destinationID Description Immediately tries to transmit continuously after Acknowledge is sent, if "1" is set (Used for Phy Read and Lock Response.) Transmit speed 00: 100Mbps; 01: 200Mbps; 10: 400Mbps; 11: Reserved Transaction Label. Used as a pair with response packet relative to request packet. This packet's Retry Code. 00: New; 01: Retry-A, 10: Retry-A, 11: Retry-B This packet's Transaction Code. This packet's Priority Level. For values other than "0", the transmitter uses Priority Arbitration relative to this packet. Indicates this packet's Destination bus number in 10 bits and the Node number in 6 bits. destinationOffsetHigh, Two continuous such areas indicate Destination Node address space address. destinationOffsetLow This address must be in quadlet units. quadlet data rCode dataLength extendedtCode Writes transmit data for Quadlet Write requests and Quadlet Read response. Response Code for Quadlet Response packet. Writes how many bytes requested for Block Read request. Specifies actual Lock Action performed by this packet data when tCode is a Lock Transaction. Writes transmitted data. This data is not written in FIFO when dataLength = "0". The first byte of the block must indicate the upper byte of the first data, regardless of data Destination or Source listing. block data - 56 - CXD1948R 6-5-1-4. Unformatted Transmit (Phy Configuration Packet) The data format for unformatted transmit during Phy Configuration packet transmit is shown below. The 1st quadlet contains packet control information. The remaining quadlets contain data, and get on the bus and are transmitted regardless of format. There is no CRC attached to the packet data. Further, there is no CRC attached to the first quadlet. Logical-inverse is not added at Link Core, so it must be added when transmitting. Unformatted Transmit Format 1 (PHY configuration Packet) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spd 00 phy_ID RT gap_cnt 0000 0000 1 tCode = 1110 0000 priority 0000 logical inverse of 2nd quadlet data Unformatted Transmit (PHY Configuration Packet) Fields Field Name 00 phy_ID R T gap_cnt Description Indicates that the transmit packet is a Phy configuration packet. Sets the force_root bit of the node with this Phy_ID sets to "1". (Only valid when R is set at "1".) Sets the force_root bit of the node with this Phy_ID to "1" when set at "1", and clears other nodes' force_root bit. The Phy_ID area is ignored when set at "0". When set to "1", all nodes use the value of the gap_cnt field to reset their own gap_Count values. Indicates values of all node new Phy_CONFIGURATION.gap_Count. This value becomes valid when it is received. (when the T field is "1") - 57 - CXD1948R 6-5-1-5. Unformatted Transmit (Link-on Packet) The data format for unformatted transmit during Link-on packet transmit is shown below. The 1st quadlet contains packet control information. The remaining quadlets contain data, and are transmitted regardless of format. There is no CRC attached to the packet data. Further, there is no CRC attached to the first quadlet. Logical-inverse is not added at Link Core, so it must be added when transmitting. Unformatted Transmit Format 1 (Link-on Packet) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spd 01 phy_ID 0000 0000 0000 0000 1 tCode = 1110 0000 priority 0000 logical inverse of 2nd quadlet data Unformatted Transmit (Link-on Packet) Fields Field Name 01 phy_ID Description Indicates that the transmit packet is a Link-on packet. Indicates the Phy chip ID of this packet's Destination. - 58 - CXD1948R 6-5-2. Asynchronous Receive (CXD1948R Host Bus) The following are the three basic formats for asynchronous data during receive. a) No-data Packets (Used for quadlet read requests and all write responses.) b) Quadlet Packets (Used for quadlet write requests, quadlet read request and block read responses.) c) Block Packets (Used for lock requests, lock responses, block write requests and block read responses.) The names of receive data areas and their contents are given below. Async Receive Fields Field Name destinationID tLabel rt tCode priority sourceID Description This node's bus number (all "0" if "local bus") and node number (all "1" if broadcast) Transaction Label. Used as a pair with response packet relative to request packet. This packet's Retry Code. 00: New; 01: Retry-X, 10: Retry-A, 11: Retry-B This packet's Transaction Code This packet's Priority Level The Node ID of the node that sent this packet destinationOffsetHigh, Two continuous such areas indicate Destination Node address space address. destinationOffsetLow This address must be in quadlet units. rCode quadlet data dataLength extendedtCode Response Code for Response packet Received data is written for quadlet write requests and quadlet read response. The number of bytes in received block type's packet data. Specifies actual Lock Action performed by this packet data when tCode is a Lock Transaction. Received data is written. This data is not written in FIFO when dataLength = "0". The first byte of the block must indicate the upper byte of the first data, regardless of data destination or Source listing. Speed of received packet. 00: 100Mbps; 01: 200Mbps; 10: 400Mbps; 11: Reserved Acknowledge code sent by Link Core relative to this packet is written. block data spd ackSent - 59 - CXD1948R 6-5-2-1. No-data Receive The data format for no-data receive is shown below. The 1st quadlet contains the destination ID and other packet headers. The 2nd and 3rd quadlets contain 16-bit source ID, and 48-bit destination offset for request and the Response Code for response. The last quadlet contains packet receive status. Quadlet Read Request Receive Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationID sourceID destinationOffsetLow spd acksent tLabel rt tCode priority destinationOffsetHigh Write Response Receive Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationID sourceID tLabel rCode rt tCode priority spd acksent - 60 - CXD1948R 6-5-2-2. Quadlet Receive The format for Quadlet Receive is shown below. The 1st quadlet contains the destination ID and other packet headers. The 2nd and 3rd quadlets contain 16-bit source ID, and 48-bit destination offset for request and the Response Code for response. The 4th quadlet contains data for Read request and Write Quadlet request, and data length and Reserved for Block Read request. The last quadlet contains packet receive status. Quadlet Write Request Receive Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationID sourceID destinationOffsetLow quadlet data spd acksent tLabel rt tCode priority destinationOffsetHigh Quadlet Read Response Receive Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationID sourceID tLabel rCode rt tCode priority quadlet data spd acksent Block Read Request Receive Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationID sourceID destinationOffsetLow dataLength spd acksent tLabel rt tCode priority destinationOffsetHigh - 61 - CXD1948R 6-5-2-3. Block Receive The format for Block Receive is shown below. The 1st quadlet contains the destination ID and other packet headers. The 2nd and 3rd quadlets contain 16-bit source ID, and 48-bit destination offset for request and the Response Code for response. The 4th quadlet contains data length and Extended Transaction Code (all "0" except for Lock Transaction). This is followed by Block data. The last quadlet contains packet receive status. Block Receive Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationID sourceID destinationOffsetLow dataLength extendedtCode tLabel rt tCode priority destinationOffsetHigh block data spd acksent Block Read or Lock Response Receive Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationID sourceID tLabel rCode rt tCode priority dataLength extendedtCode block data spd acksent 6-6. Self-ID Packet Receiving Error Processing In the Self-ID phase after bus reset on the CXD1948R, if the Self-ID packet could not be received correctly, Self-ID packet receive is stopped immediately and the Node_sum value becomes "0". The external microcomputer thus can judge that the Self-ID phase could not be completed correctly. - 62 - CXD1948R 7. Insert Packet 7-1. Insert Packet Transmission The CXD1948R has a function where the data set by the host I/F is inserted as isochronous packet and it is transmitted when the transport stream data is being isochronous-transmitted. The transmit method is the same as for asynchronous packet transmit; it is done by accessing the specified CFR (refer to CFR Address Map) address (64 to 6C). * Insert Packet Transmit The external writes packet data in the CXD1948R internal IPF in order to perform insert packet transmit. At this time only the first quadlet of the packet is written in the CFR IPBWrite (first quadlet of the packet) register (64h). The second through the next to the last quadlets are written in the CFR IPBWrite register (68h). Then the last quadlet is written in the IPBWrite (confirm write) register (6Ch) to store the packet in IPB. There are two types of Insert packet transmission, as described below. (1) Transmission by writing the last quadlet in IPBWrite (confirm write). (2) Transmission by setting the CFR IPTxGo register to high. If IPTxGo is used, the data written earlier in IPB can be transmitted as is, with no changes. The IPTxGo register only becomes "0" when Insert packet transmit is actually performed, or if it is erased from IPB due to transmit Late processing or the like. The time stamp added to the Insert packet takes the fall timing of the Packet Gap input directly after IPTxGo register value changes from "0" to "1". Once the time stamp is added, processing is the same as for transport stream data. The FIFO capacity for the Insert packet is 188 bytes. Data which exceeds this capacity can not be transmitted. In this case, the data up to 188 bytes is valid. If the transmitted data is less than 188 bytes, all data bits other than those written are set to "1" and transmitted. The written data is held after transmit, and to continue sending a packet with the same contents, it is only necessary to set the IPTxGo register to "1" after confirming that it changed to "0". Writing to IPB must be done in quadlet units. The procedure for transmitting a 4 quadlet Insert packet is described below. (for 8 bit interface) (1) Confirming that transmit of the previously written packet is complete The CFR Control register (08h to 0bh) is read to confirm that its first bit (IPTxGo bit) is low. If it is high, it means that transmit of the previously written packet has not been performed. XCS ADDRESS 08h 09h 0Ah 0Bh XW/R DATA xxxxxx1xb This indicates that the Insert packet has not been transmitted. It is "xxxxxx0xB" when an Insert packet can be written. - 63 - CXD1948R (2) First quadlet of the transmitted packet Write Let the first quadlet of the quadlet write request packet be "00000000h". This is written in the CFR IPBWrite (first quadlet of the packet) register. XCS ADDRESS 64h 65h 66h 67h XW/R DATA 00h 00h 00h 00h (3) Second quadlet of the transmitted packet Write Let the second quadlet of the quadlet write request packet be "FFC1FFFFh". This is written in the CFR IPBWrite register. XCS ADDRESS 68h 69h 6Ah 6Bh XW/R DATA FFh FFh C1h FFh (4) Third quadlet of the transmitted packet Write Let the third quadlet of the quadlet write request packet be "F000000Ch". This is written in the CFR IPBWrite register. XCS ADDRESS 68h 69h 6Ah 6Bh XW/R DATA 0Ch 00h 00h F0h - 64 - CXD1948R (5) Last quadlet of the transmitted packet Write Let the last quadlet of the quadlet write request packet be "12345678h". This is written in the CFR IPBWrite (confirm write) register. XCS ADDRESS 6Ch 6Dh 6Eh 6Fh XW/R DATA 78h 56h 34h 12h The 4-quadlet data is stored in the IPB as shown above. The CXD1948R transmits the packet with 1394 header and CIP header automatically attached, as with the case for the normal transport stream data, after the time stamp is added to the packet stored in the IPB. If Insert packet transmit does not take place due to Late processing, the CFR interrupt register (0Ch to 0Fh) must be read to confirm that the IpktLate bit is high. Set the CFR IPTxGo register to high to add the time stamp when transmitting the Insert packet data again without updating its contents. - 65 - CXD1948R 7-2. Adding a Time Stamp to the Insert Packet A time stamp must be added to the Insert packet in order to process it as an isochronous packet. The CXD1948R adds the time stamp using PACKETGAP input. Concretely, the TxDelay register value added at the falling edge of the PACKETGAP input immediately after the Insert packet has been written to the IPB becomes the time stamp value of the Insert packet to be transmitted. The time stamp must be added to the Insert packet during the interval when there is no transport stream data input. When transmitting the entire transport stream, there is no gap during which to input PACKETGAP, so the Insert packet cannot be transmitted. When transmitting the Insert packet, be sure to select a program from the transport stream and then perform transmission. At this time, PACKETGAP input can add the time stamp to the Insert packet by inputting the PACKETEN of the non-selected programs as is. When transmitting the entire transport stream PACKETEN AIDT Program 1 Program 2 Program 1 Program 3 When transmitting only program 1 within the transport stream PACKETEN AIDT Program 1 Program 2 Program 1 Program 3 PACKETGAP - 66 - CXD1948R 8. Link-Phy Communication 8-1. Link-Phy Interface Specifications The CXD1948R and Phy layer chip communicate using the four signals shown in the block diagram below: D [0 : 3], CTL [0 : 1], LREQ and SYSCLK. D [0 : 3] CTL [0 : 1] 1394 Link Layer CXD1948R 1394 Phy Layer LREQ SYSCLK The roles of the signals are as follows. D [0 : 3] in/out Bidirectional data line CTL [0 : 1] in/out Bidirectional control line LREQ out LREQ out Request signal line from CXD1948R to Phy chip. Used for bus access and Phy register read/write requests. SYSCLK in System clock (49.152MHz) supplied from Phy to the CXD1948R. The types of communication and their contents are described below. 8-2. Communication There are four types of communication between Phy Link: Request, Status, Transmit and Receive. Except for request, all commands are initialized by the Phy chip. 8-2-1. Bus controlling CTL [0 : 1] controls communication between Phy and the CXD1948R. The communication contents differ depending on if Phy or the CXD1948R is controlling. a) Phy controlling CTL [0 : 1] 00 01 10 11 Name Idle Status Receive Transmit Bus is idle (Default mode) Phy is sending status information to the CXD1948R Phy is sending a packet to the CXD1948R The CXD1948R authorized packet transmit Description of Activity b) CXD1948R controlling CTL [0 : 1] 00 01 10 11 Name Idle Hold Transmit Reserved Description of Activity The CXD1948R completed transmit The CXD1948R is holding the bus until transmit preparations are complete. Or, the CXD1948R is trying to transmit another packet without arbitration. The CXD1948R is transmitting a packet to Phy Not used - 67 - CXD1948R 8-2-2. Request The CXD1948R always uses serial communication of LREQ to send a request to Phy when a request to the bus or access to the Phy register is required. There are three types of request: Bus Request, Read Register Request and Write Register Request. The timing chart and contents are illustrated below. LR0 LR1 LR2 LR3 LR (n - 2) LR (n - 1) a) Bus Request (length of stream: 7 bits) Bit 0 1 to 3 4 to 5 6 Name Start Bit Request Type Transmit start bit. Always "1". Indicates type of request. (Refer to Request Type table.) Description Request Speed Indicates request communication speed. (Refer to Request Speed table.) Stop Bit Last transmit bit. Always "0". b) Read Register Request (length of stream: 9 bits) Bit 0 1 to 3 4 to 7 8 Name Start Bit Request Type Address Stop Bit Transmit start bit. Always "1". Indicates type of request. (Refer to Request Type table.) Address for Phy register read. Last transmit bit. Always "0". Description c) Write Register Request (length of stream: 17 bits) Bit 0 1 to 3 4 to 7 8 to 15 16 Name Start Bit Request Type Address Data Stop Bit Transmit start bit. Always "1". Indicates type of request. (Refer to Request Type table.) Address for Phy register write. Write data for Phy register specified by Address. Last transmit bit. Always "0". Description - 68 - CXD1948R Request Type LREQ [1 : 3] Name Description Immediate bus acquisition request. To output Ack for an asynchronous packet reception, immediate bus acquisition is requested without arbitration when Idle is detected. Used to transmit Acknowledge. Isochronous request. Requests execution of arbitration. Used for isochronous transmit. Priority request. Requests arbitration after Subaction Gap, ignoring Fair protocol. Used for Cycle Master request. Fair request Requests execution of arbitration after subaction gap according to fair protocol. Used for Fair transmit. Read request. Requests return of register contents according to Status Transfer. Write request. Requests write to specified address. Reserved. 000 ImmReq 001 IsoReq 010 PriReq 011 FairReq 100 101 110, 111 RdReq WrReq Reserved Request Speed LREQ [4 : 5] 00 01 10 11 Data Rate 100Mb/s 200Mb/s 400Mb/s Reserved 8-2-2-1. Bus Request In order to access Fair or Priority, waits at least 1 clock after the CXD1948R becomes idle to send the request. When the CTL pin is in receive state (CTL [0 : 1] = 10), CXD1948R interprets the request as being refused. It is reissued 1 clock after the next idle state. In the Cycle Master node, the cycle start message is sent using Priority Request. In order to request sending of isochronous data, the CXD1948R can issue an isochronous request after receiving cycle start. Phy clears the isochronous request only after the bus is acquired successfully. The CXD1948R must issue ImmReq while it is receiving a packet addressed to itself in order to send Acknowledge. When packet reception is completed, Phy immediately acquires the bus and gives authorization to the CXD1948R. If the header CRC is not erroneous, the CXD1948R returns an Acknowledge signal. However, if the header CRC is erroneous, the CXD1948R immediately releases the bus. The CXD1948R can not use this authorization to send other packets. In order to ensure this operation, the CXD1948R waits 160ns after the completion of packet reception. Then Phy acquires the bus once again, and a CRC error Acknowledge is sent. Then it releases the bus and continues with another request. - 69 - CXD1948R Consider a case in which two different nodes confirm that the packet sent is addressed to them (one is correct, one is wrong), and both nodes issue an ImmReq before CRC check. The Phy of both nodes try to capture the bus immediately after packet receive is completed. At this time, there will be a momentary collision on the local bus. This can be detected by all of the Phy connected to the bus. This collision is not interpreted as Bus Reset, but as high impedance state. After CRC check is completed, the wrong node will withdraw its request and the high impedance state is discontinued. The expected Acknowledge is lost as a side effect of this, but is processed by the host protocol. 8-2-2-2. Read/Write Request When the CXD1948R requests reading of a specific register's contents, Phy transmits the register contents to the CXD1948R by Status Transfer. Even if packets are received while Phy is sending status information to the CXD1948R, Phy continues processing until the register contents are transferred. For a Write Request, Phy loads the data fields into the appropriate register as soon as transmission is completed. The CXD1948R can read/write at any time. 8-2-3. Status Status transmission is started by Phy when it has some data to transmit to the CXD1948R. Phy begins transmission by simultaneously setting CTL [0 : 1] to "01b" and the first 2 bits of Status information to D [0: 1]. Phy maintains CTL = Status during status transmission. Phy may finish Status transmission early by setting the CTL value to some other value. This happens if a packet arrives before Status transmit is completed. When such an interruption occurs, Phy repeatedly tries resending until the transfer is successful. There must be at least one idle cycle in a continuous Status transmission. Phy normally sends the first four bits of Status to the CXD1948R. These bits are the Status Flags required for the CXD1948R state machine. When transmission of a request containing a Read Request is completed, or when Phy has information to send to the CXD1948R or the transaction layer, Phy sends the first Status packet to the CXD1948R. The only state in which Phy sends register contents automatically to the CXD1948R is that after completion of Self-Identification, and Physical_ID register contents containing a new node address are transmitted. The transmit timing and bit definitions are illustrated below. PHY Ctl [0 : 1] 00 01 01 01 00 00 PHY D [0 : 1] 00 S [0, 1] S [2, 3] S [14, 15] 00 00 - 70 - CXD1948R Status bit (Length of stream: 16 bits) Bit 0 1 2 3 Name Arbitration Reset Gap Subaction Gap Bus Reset State Time-out Description Indicates detection of idle state, for Bus Arbitration Reset Gap Time. This bit is used by the CXD1948R busy/retry state machine. Indicates detection of idle state, for Subaction Gap Time. This bit is used by the CXD1948R to detect the end of the isochronous cycle. Indicates Phy in bus reset state. Indicates that Phy state machine is stopped in a certain state for a long time. Normally used for cable topology loop detection. Holds the address of the register being read when Phy is trying to send register contents to CXD1948R; for example, when responding to Read via the LREQ pin. Holds the register being sent to CXD1948R. 4 to 7 8 to 15 Address Data 8-2-4. Transmit When the CXD1948R requests bus access via the LREQ pin, Phy performs arbitration for bus access. When Phy wins the arbitration, Transmit is sent to the CTL pin for at least 1 SYSCLK cycle, and Idle is then asserted for 1 cycle to give the CXD1948R the bus. After detecting transmit state from Phy, the CXD1948R asserts either Hold or Transmit to the CTL pins to take over interface control. The CXD1948R asserts Hold until the data is ready, in order to keep bus initiative. During this time, Phy asserts Data-on state to the bus. When the packet is ready to transmit , the CXD1948R transmits the first bit of the packet, and at the same time asserts Transmit to the CTL pins. After sending the last bit of the packet, the CXD1948R asserts either Idle or Hold to the CTL pins for 1 cycle. Then it asserts Idle for 1 cycle before these pins become high impedance. Here, when it is necessary for the CXD1948R to send another packet without releasing the bus, it indicates Hold to Pht. In response to this, Phy asserts Transmit in the same way as before after waiting for the minimum required time. This function is used when multiple isochronous packets are sent in succession to different channels without the CXD1948R releasing the bus, and when a Response packet is sent following Acknowledge. When in this way multiple transmissions are performed in succession, all transmissions are at the same speed. This is because the speed is set at the time of arbitration to acquire the bus, and in successive transmissions intermediate arbitrations are skipped. As described above, when the CXD1948R completes sending the last packet on the newest bus initiative, it releases the bus by asserting Idle to the CTL pins for 2 Sclk. When Phy detects Idle from the CXD1948R, it starts to assert Idle to CTL for 1 clock. - 71 - CXD1948R The timing chart for transmit is shown below. Single Packet PHY Ctl [0 : 1] 00 11 00 ZZ ZZ ZZ ZZ ZZ ZZ ZZ ZZ 00 PHY D [0 : 3] 00 00 00 ZZ ZZ ZZ ZZ ZZ ZZ ZZ ZZ 00 CXD1948R Ctl [0 : 1] ZZ ZZ ZZ 01 01 10 10 10 10 00 00 ZZ CXD1948R D [0 : 3] ZZ ZZ ZZ 00 00 D0 D1 D2 Dn 00 00 ZZ Continued Packet PHY Ctl [0 : 1] ZZ ZZ ZZ ZZ 00 00 11 00 ZZ ZZ ZZ ZZ PHY D [0 : 3] ZZ ZZ ZZ ZZ 00 00 00 00 ZZ ZZ ZZ ZZ CXD1948R Ctl [0 : 1] 10 10 01 00 ZZ ZZ ZZ ZZ 01 01 10 10 CXD1948R D [0 : 3] Dn-1 Dn 00 00 ZZ ZZ ZZ ZZ 00 00 D0 D1 ZZ: High-impedance state, D0 to Dn: packet data - 72 - CXD1948R 8-2-5. Receive When data from the bus is received at Phy, it is sent from Phy to the CXD1948R in the following order. Phy asserts Receive to the CTL pins and "all1" to the D pin. Phy indicates the start of the packet by placing a speed code on the D pin. Next it indicates the contents of the packet, and until transmission of the last symbol in the packet is completed, it holds the CTL pins at Receive. Phy indicates the end of the packet by asserting Idle to the CTL pins. The speed code is specified by Phy-Link protocol, and does not include CRC calculation or other data protect. Phy can identify if there is data on the bus or not without looking at the packet. This also applies if a packet is being sent at a faster speed than Phy can receive. In this case, the packet is completed by asserting Idle when the Data-on state is completed. If Phy supports a faster transmission speed than the CXD1948R, the CXD1948R detects the speed code and ignores the packet until it becomes Idle again. The timing chart for reception is illustrated below. PHY Ctl [0 : 1] (binary) 00 10 10 10 10 10 10 00 00 PHY D [0 : 3] (hex) 00 F F SP D0 D1 Dn 00 00 Note: SP means Speed Code. Speed codes for receive D [0 : 3] 00xx 0100 Data Rate 100Mbit/s 200Mbit/s Note 1: "xx" means that "0" was transmitted, but it is ignored for receive. Note 2: This LSI supports 100Mbit/s and 200Mbit/s communications. - 73 - CXD1948R 9. Parallel Input/Output Port The CXD1948R has a 5-bit I/O port. The direction of each port and the value during output mode can be set and the value during input mode can be read by accessing the CFR using the host interface. The status after initializing the CXD1948R is input mode for all ports. Symbol PORT0 PORT1 PORT2 PORT3 PORT4 Pin No. 44 45 46 69 70 CFR register name Direction switching PDIR0 PDIR1 PDIR2 PDIR3 PDIR4 Value setting (output)/value reading (input) PDATA0 PDATA1 PDATA2 PDATA3 PDATA4 Ports are set to output mode when the corresponding PDIR register is "1", and to input mode when "0". Concretely, when PDIR0 is set to "1", the value set in the PDATA0 register is output from the PORT0 pin. If PDIR0 is set to "0", the value input to the PORT0 pin is loaded to the PDATA0 register. Each I/O port can be set independently. - 74 - 10. System Configuration Example HOST Interface 8bit Application Interface 8bit/asynchronous/ERRFLAG not used HOST CTL [0 : 1] XRESET X8/16 LREQ XCS XW/R XWAIT XINT ADDRESS [6 : 0] DATA [7 : 0] D [0 : 3] - 75 - CXD1948R AIWRITE AIREAD PACKETEN READREQ AIDT [7 : 0] LPS SYSCLK PACKETGAP IOEC IEEE1394 PHY LSI MPEG2 Transporter CXD1948R CXD1948R Annex. Corresponding Table for CFR Access Address And Host Interface I/O Data (8-bit Mode) 76543210765432107654321076543210 03h 07h 0bh 0fh 13h 17h 1bh 1fh 23h 27h 2bh 2fh 33h 37h 3bh 3fh 43h 47h 4bh 4fh 53h 67h 6bh 6fh 73h 77h 7fh 02h 06h 0ah 0eh 12h 16h 1ah 1eh 22h 26h 2ah 2eh 32h 36h 3ah 3eh 42h 46h 4ah 4eh 52h 66h 6ah 6eh 72h 76h 7eh 01h 05h 09h 0dh 11h 15h 19h 1dh 21h 25h 29h 2dh 31h 35h 39h 3dh 41h 45h 49h 4dh 51h 65h 69h 6dh 71h 75h 7dh 00h 04h 08h 0ch 10h 14h 18h 1ch 20h 24h 28h 2ch 30h 34h 38h 3ch 40h 44h 48h 4ch 50h 64h 68h 6ch 70h 74h 7ch I/O data bit Version Node Address Control Interrupt Interrupt Mask Cycle Timer DIF Mode Iso TxRx Init Diagnostics Async Status Phy Chip Access Parallel Port Tx1394Hdr TxCIPHdr1 TxCIPHdr2 SPH-rsv/AddData1 to 2 AddData3 to 6 AddData7 to 10 Rx1394Hdr RxCIPHdr1 RxCIPHdr2 IPB Write (first) IPB Write IPB Write (confirm) ATF Write (first) IPB Write ARF Read ATF Write (confirm) - 76 - CXD1948R Annex. Corresponding Table for CFR Access Address And Host Interface I/O Data (16-bit Mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 02h 06h 0ah 0eh 12h 16h 1ah 1eh 22h 26h 2ah 2eh 32h 36h 3ah 3eh 42h 46h 4ah 4eh 52h 66h 6ah 6eh 72h 76h 7eh 00h 04h 08h 0ch 10h 14h 18h 1ch 20h 24h 28h 2ch 30h 34h 38h 3ch 40h 44h 48h 4ch 50h 64h 68h 6ch 70h 74h 7ch I/O data bit Version Node Address Control Interrupt Interrupt Mask Cycle Timer DIF Mode Iso TxRx Init Diagnostics Async Status Phy Chip Access Parallel Port Tx1394Hdr TxCIPHdr1 TxCIPHdr2 SPH-rsv/AddData1 to 2 AddData3 to 6 AddData7 to 10 Rx1394Hdr RxCIPHdr1 RxCIPHdr2 IPB Write (first) IPB Write IPB Write (confirm) ATF Write (first) IPB Write ARF Read ATF Write (confirm) - 77 - CXD1948R Package Outline Unit: mm 100PIN LQFP (PLASTIC) 16.0 0.2 75 76 14.0 0.1 51 50 100 1 0.5 0.08 + 0.08 0.18 - 0.03 25 26 (0.22) + 0.2 1.5 - 0.1 + 0.05 0.127 - 0.02 0.1 0.1 0.1 0 to 10 DETAIL A 0.5 0.2 NOTE: Dimension "" does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY/PHENOL RESIN SOLDER PLATING 42 ALLOY LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT SONY CODE EIAJ CODE JEDEC CODE LQFP-100P-L01 QFP100-P-1414-A - 78 - 0.5 0.2 A (15.0) |
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